soc: nxp: imxrt10xx: support configuration of SYSPLL using devicetree

dts/arm/nxp/nxp_rt1040.dtsi

@@ -11,7 +11,7 @@
 };
 
 &sysclk {
-	clock-frequency = <500000000>;
+	clock-frequency = <528000000>;
 };
 
 &ccm {
@@ -20,10 +20,13 @@
 	};
 
 	arm-podf {
-		clock-div = <2>;
+		clock-div = <1>;
 	};
 };
 
+&gpt2 {
+	gptfreq = <33000000>;
+};
 
 / {
 	soc {

dts/arm/nxp/nxp_rt10xx.dtsi

@@ -297,6 +297,15 @@
 				#clock-cells = <0>;
 			};
 
+			sys-pll {
+				compatible = "nxp,imx-ccm-fnpll";
+				loop-div = <22>;
+				numerator = <0>;
+				denominator = <1>;
+				src = <0>;
+				#clock-cells = <0>;
+			};
+
 			#clock-cells = <3>;
 		};
 

dts/bindings/clock/nxp,imx-ccm-fnpll.yaml

@@ -0,0 +1,38 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  i.MX CCM Fractional PLL. Output frequency is given by the following
+  formula: Fout = Fin * (loop-div + (numerator/denominator)
+
+compatible: "nxp,imx-ccm-fnpll"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  "#clock-cells":
+    const: 0
+
+  loop-div:
+    type: int
+    required: true
+    description: |
+      Loop divider. Divides PLL feedback loop (effectively multiplying output
+      frequency)
+
+  numerator:
+    type: int
+    required: true
+    description: |
+      Numerator of PLL multiplier fraction
+
+  denominator:
+    type: int
+    required: true
+    description: |
+      Denominator of PLL multiplier fraction
+
+  src:
+    type: int
+    required: true
+    description: Sets source for PLL input. SOC specific.

soc/nxp/imxrt/Kconfig

@@ -184,6 +184,9 @@ config INIT_ENET_PLL
 	  MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
 	  for MIMXRT1021").
 
+config INIT_SYS_PLL
+	bool "Initialize System PLL"
+
 endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
 
 endif # SOC_FAMILY_NXP_IMXRT

soc/nxp/imxrt/imxrt10xx/Kconfig

@@ -70,6 +70,7 @@ config SOC_MIMXRT1042
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ARM_MPU
 	select INIT_ARM_PLL
+	select INIT_SYS_PLL
 
 config SOC_MIMXRT1051
 	select HAS_MCUX_ENET

soc/nxp/imxrt/imxrt10xx/soc.c

@@ -40,6 +40,16 @@ const clock_arm_pll_config_t armPllConfig = {
 };
 #endif
 
+#if CONFIG_INIT_SYS_PLL
+/* Configure System PLL */
+const clock_sys_pll_config_t sysPllConfig = {
+	.loopDivider = (DT_PROP(DT_CHILD(CCM_NODE, sys_pll), loop_div) - 20) / 2,
+	.numerator = DT_PROP(DT_CHILD(CCM_NODE, sys_pll), numerator),
+	.denominator = DT_PROP(DT_CHILD(CCM_NODE, sys_pll), denominator),
+	.src = DT_PROP(DT_CHILD(CCM_NODE, sys_pll), src),
+};
+#endif
+
 #if CONFIG_USB_DC_NXP_EHCI
 /* USB PHY condfiguration */
 #define BOARD_USB_PHY_D_CAL (0x0CU)
@@ -160,6 +170,10 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_InitVideoPll(&videoPllConfig);
 #endif
 
+#if CONFIG_INIT_SYS_PLL
+	CLOCK_InitSysPll(&sysPllConfig);
+#endif
+
 #if DT_NODE_EXISTS(DT_CHILD(CCM_NODE, arm_podf))
 	/* Set ARM PODF */
 	BUILD_ASSERT_PODF_IN_RANGE(arm_podf, 1, 8);
@@ -172,8 +186,13 @@ static ALWAYS_INLINE void clock_init(void)
 	BUILD_ASSERT_PODF_IN_RANGE(ipg_podf, 1, 4);
 	CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1);
 
+#ifdef CONFIG_SOC_MIMXRT1042
+	/* Set PRE_PERIPH_CLK to SYS_PLL */
+	CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x0);
+#else
 	/* Set PRE_PERIPH_CLK to PLL1, 1200M */
 	CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);
+#endif
 
 	/* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
 	CLOCK_SetMux(kCLOCK_PeriphMux, 0x0);