Trying to get litex_vexriscv core working on a lattice ecp5 with 8mb ram with zephyr

[kenkit]

Describe the bug

I managed to build the core by using the official docs and confimed it's working as below:
I went ahead and followed the documetation here to generate the bitstream for the board https://docs.zephyrproject.org/latest/boards/enjoydigital/litex_vexriscv/doc/index.html
Everything went well.

Now proceeded to create a simple hello world where it should just print hello world from the samples in zephyr but I don't get anything on the serial output after loading the kernel via litex_term
I did get a warning while generating building the application using the dts file

Here is my overlay.dts file created with the following options

&cpu0 {
    clock-frequency = <25000000>;
};
&ctrl0 {
    reg = <0xf0000000 0x4>,
        <0xf0000004 0x4>,
        <0xf0000008 0x4>;
    reg-names = "reset",
        "scratch",
        "bus_errors";
    };
&uart0 {
    reg = <0xf0004800 0x4>,
        <0xf0004804 0x4>,
        <0xf0004808 0x4>,
        <0xf000480c 0x4>,
        <0xf0004810 0x4>,
        <0xf0004814 0x4>,
        <0xf0004818 0x4>,
        <0xf000481c 0x4>;
    reg-names = "rxtx",
        "txfull",
        "rxempty",
        "ev_status",
        "ev_pending",
        "ev_enable",
        "txempty",
        "rxfull";
    interrupts = <0 0>;
};
&timer0 {
    reg = <0xf0004000 0x4>,
        <0xf0004004 0x4>,
        <0xf0004008 0x4>,
        <0xf000400c 0x4>,
        <0xf0004010 0x4>,
        <0xf0004014 0x4>,
        <0xf0004018 0x4>,
        <0xf000401c 0x4>;
    reg-names = "load",
        "reload",
        "en",
        "update_value",
        "value",
        "ev_status",
        "ev_pending",
        "ev_enable";
    interrupts = <1 0>;
};
&eth0 {
    reg = <0xf0000800 0x4>,
        <0xf0000804 0x4>,
        <0xf0000808 0x4>,
        <0xf000080c 0x4>,
        <0xf0000810 0x4>,
        <0xf0000814 0x4>,
        <0xf0000818 0x4>,
        <0xf000081c 0x4>,
        <0xf0000820 0x4>,
        <0xf0000824 0x4>,
        <0xf0000828 0x4>,
        <0xf000082c 0x4>,
        <0xf0000830 0x4>,
        <0xf0000834 0x4>,
        <0x80000000 0x1000>,
        <0x80001000 0x1000>;
    reg-names = "rx_slot",
        "rx_length",
        "rx_errors",
        "rx_ev_status",
        "rx_ev_pending",
        "rx_ev_enable",
        "tx_start",
        "tx_ready",
        "tx_level",
        "tx_slot",
        "tx_length",
        "tx_ev_status",
        "tx_ev_pending",
        "tx_ev_enable",
        "rx_buffers",
        "tx_buffers";
    interrupts = <2 0>;
};
&mdio0 {
    reg = <0xf0001008 0x4>,
        <0xf000100c 0x4>;
    reg-names = "w",
        "r";
};
&spi0 {
    status = "disabled";
};
&spi1 {
    reg = <0xf0003000 0x4>,
        <0xf0003800 0x4>,
        <0x20000000 0x400000>;
    reg-names = "core_mmap_dummy_bits",
        "phy_clk_divisor",
        "flash_mmap";
    clock-frequency = <12500000>;
};
&i2c0 {
    status = "disabled";
};
&i2s_rx {
    status = "disabled";
};
&i2s_tx {
    status = "disabled";
};
&wdt0 {
    status = "disabled";
};
&clock0 {
    status = "disabled";
};
&ram0 {
    reg = <0x40000000 0x800000>;
};
&dna0 {
    status = "disabled";
};
&prbs0 {
    status = "disabled";
};

Build the target:

python3 -m litex_boards.targets.colorlight_5a_75x --build --board=5a-75b --revision=8.2 --with-ethernet --eth-ip 192.168.2.1 --eth-phy 0 --sys-clk-freq 25e6 --use-internal-os --cpu-type=vexriscv --csr-json csr.json

Generate the dts and config overlay:

python3 -m litex.tools.litex_json2dts_zephyr --dts overlay.dts --config overlay.config csr.json

BUILD THE EXAMPLE PROJECT

ken@ken-Latitude-5420:/media/mount/programming/HDLs/zephyr/my-workspace/example-application$ west build   -b litex_vexriscv  .  -DDTC_OVERLAY_FILE=overlay.dts
-- west build: generating a build system
Loading Zephyr default modules (Zephyr base (cached)).
-- Application: /media/mount/programming/HDLs/zephyr/my-workspace/example-application
-- CMake version: 4.0.3
-- Cache files will be written to: /home/ken/.cache/zephyr
-- Zephyr version: 4.1.99 (/media/mount/programming/HDLs/zephyr/my-workspace/zephyr)
-- Found west (found suitable version "1.4.0", minimum required is "0.14.0")
-- Board: litex_vexriscv, qualifiers: litex_vexriscv
-- Found host-tools: zephyr 0.17.1 (/home/ken/zephyr-sdk-0.17.1)
-- Found toolchain: zephyr 0.17.1 (/home/ken/zephyr-sdk-0.17.1)
-- Found BOARD.dts: /media/mount/programming/HDLs/zephyr/my-workspace/zephyr/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
-- Found devicetree overlay: overlay.dts
unit address and first address in 'reg' (0xf0000000) don't match for /soc/soc_controller@e0000000
unit address and first address in 'reg' (0xf0003800) don't match for /soc/serial@e0001800
unit address and first address in 'reg' (0xf0003000) don't match for /soc/timer@e0002800
unit address and first address in 'reg' (0xf0001008) don't match for /soc/mdio@e0008000
unit address and first address in 'reg' (0xf0000800) don't match for /soc/ethernet@e0009800
-- Generated zephyr.dts: /media/mount/programming/HDLs/zephyr/my-workspace/example-application/build/zephyr/zephyr.dts
-- Generated pickled edt: /media/mount/programming/HDLs/zephyr/my-workspace/example-application/build/zephyr/edt.pickle

BUT THE IMAGE DOES NOT BOOT
This is output of the core without loading anything,
after completing upload via serialboot it just freezes there

ken@ken-Latitude-5420:/media/mount/programming/HDLs/zephyr/my-workspace/example-application/build/zephyr$ litex_term /dev/ttyUSB5 --speed 115200 
ARP failed
Booting from boot.bin...
Copying boot.bin to 0x40000000... ARP failed

Network boot failed.
No boot medium found

--============= Console ================--

litex> help


LiteX BIOS, available commands:

leds                     - Set Leds value
flush_cpu_dcache         - Flush CPU data cache
crc                      - Compute CRC32 of a part of the address space
ident                    - Identifier of the system
help                     - Print this help

netboot                  - Boot via Ethernet (TFTP)
serialboot               - Boot from Serial (SFL)
reboot                   - Reboot
boot                     - Boot from Memory

mem_cmp                  - Compare memory content
mem_speed                - Test memory speed
mem_test                 - Test memory access
mem_copy                 - Copy address space
mem_write                - Write address space
mem_read                 - Read address space
mem_list                 - List available memory regions

sdram_mr_write           - Write SDRAM Mode Register
sdram_test               - Test SDRAM
sdram_init               - Initialize SDRAM (Init + Calibration)

mdio_dump                - Dump MDIO registers
mdio_read                - Read MDIO register
mdio_write               - Write MDIO register


litex> mem_list

Available memory regions:
OPENSBI    0x40f00000 0x80000 
PLIC       0xf0c00000 0x400000 
CLINT      0xf0010000 0x10000 
ROM        0x00000000 0x10000 
SRAM       0x10000000 0x1800 
MAIN_RAM   0x40000000 0x800000 
ETHMAC     0x80000000 0x2000 
ETHMAC_RX  0x80000000 0x1000 
ETHMAC_TX  0x80001000 0x1000 
CSR        0xf0000000 0x10000 `

Regression

• This is a regression.

Steps to reproduce

No response

Relevant log output

Impact

Annoyance – Minor irritation; no significant impact on usability or functionality.

Environment

No response

Additional Context

No response

[github-actions[bot]]

Hi @kenkit! We appreciate you submitting your first issue for our open-source project. 🌟

Even though I'm a bot, I can assure you that the whole community is genuinely grateful for your time and effort. 🤖💙