Weird behavior with MPU alignment in flash section on ARM Cortex-R5 on ZynqMP #89910
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robhancocksed
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We have a Zephyr application running on a Xilinx MPSoC (ZynqMP) platform on the Cortex-R5 (RPU) cores. Essentially the memory layout/configuration is that we have:
The problem I am seeing is that if I end up using more than 50% (i.e. 128KB) of the TCM space for text and rodata space, then things immediately start to overflow:
From what I can see from looking at the generated zephyr.map file, in this state, a bunch of padding is being inserted at the end of the rodata section:
This appears to be coming from include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld:
It looks like what this is trying to do is align the end of the rodata section (supposedly the last) to a power of 2 boundary. The problem is that (at least in this configuration?) that is NOT the last section in the flash segment, as the data section seems to be appended to it (and gets copied to DDR on startup). So if we are already past the 128KB boundary, doing this adds a bunch of padding up to the 256KB boundary before the data section, causing the data section to no longer fit in TCM.
Something does not seem right with this code. In my application, simply deleting the MPU_ALIGN seems to resolve this problem, but I assume this is not a proper solution generically. Does someone know what is going on here or the proper way to fix it?
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