Possible bug in MIMXRT1060_EVKB Devicetree, sai1 node #83882
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As written in the issues template, I am first verifying that the issue is a genuine Zephyr bug before making an issue. Describe the bug Looking at the implementation: static void enable_mclk_direction(const struct device *dev, bool dir)
{
const struct i2s_mcux_config *dev_cfg = dev->config;
uint32_t offset = dev_cfg->mclk_pin_offset;
uint32_t mask = dev_cfg->mclk_pin_mask;
uint32_t *base = (uint32_t *)(dev_cfg->mclk_control_base + offset);
if (dir) {
*base |= mask;
} else {
*base &= ~mask;
}
} And IOMUXC_EnableMode accesses GPR1 by the definition below: /** IOMUXC_GPR - Register Layout Typedef */
typedef struct {
uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
__IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
/* ...up to GPR34 */
} IOMUXC_GPR_Type; The offset in the line Expected behavior Impact Logs and console output Environment (please complete the following information):
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Replies: 2 comments
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Thank you for your detail information. I am working to prepare a patch for this bug. |
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#83978