STM32F411 dts include causes incorrect I2S peripheral clk

[tgonggia]

Hi,

I am currently trying to set up I2S on my stm32f411 blackpill board. However, despite setting everything correctly I was receiving the incorrect LRCLK when outputting the I2S signal (48KHz defined but output is 75KHz). I believe there is currently a bug in stm32f411.dtsi that includes plli2s node in stm32f401.dtsi, which has the incorrect node binding for PLL I2S. The issue is that the div-m property for plli2s is not supported on stm32f401 but is for stm32f411, so there is currently no way for user to configure this clock divider value in the device tree. In result, this will cause anyone that is using the i2s HAL module to have the incorrect I2S output clock value even if everything is configured correctly, and I had to modify the SDK file in order to get it property output 48Khz for the LRCLK.

Thanks,

[FRASTM]

can you have a look at PR #81460 and especially the commit 7b69d80fc4894f2c5f27abb76c97c9bd2d646b4e

[tgonggia]

Looks good to me! The changes in the commit are identical to what I have changed in the SDK.