Preventing or correct handling of clock switch

[P5ych0d4d]

Hello everyone. :)

I am currently trying to implement the application “Phy_802_15_4_Cli” from the STM32Cube repository in Zephyr. We are using a STM32WB55RG.
Unlike in the standard application, we use the PLL as SYSCLOCK, the input clock is HSE (32MHz).
As CLI (command line interface) we use LPUART. The aim is to use the PC app STM32CubeMonitor-RF with the "Phy_802_15_4_Cli" app on the STM32WB55, which has already worked so far.
However, the problem is that in RX mode, as soon as the first 802.15.4 packet is received, the C2DS bit is set in the PWR_EXTSCR register --> “CPU2 is in deepsleep or hold by C2BOOT”. This causes the SW and SWS bits in the RCC_CFGR register to be set from 11 (PLL as system clock) to 10 (HSE as system clock).
The output via LPUART then only produces garbage. One way to prevent the low power mode of the C2, e.g. using SHCI_C2_RADIO_AllowLowPower() only works with BLE, Thread or Zigbee, but not for the LLD_Tests.

Another attempt was to check the SYSCLOCK within the RX callback each time and reset it to PLL if it is not already.

if(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
            /* Set PLL as System Clock Source */
            LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
            while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
            }
}

This only works partially, but reduces the garbage in the output.
Does anyone have any idea how I can prevent this clock switch?

Another suggestion from @erwango was to assign a fixed clock to the LPUART like:

&lpuart1 {
    clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>,
        <&rcc STM32_SRC_LSE LPUART1_SEL(3)>;

But this is not an option to me as we would like to integrate the app into our production test, which is why the functionality with the external clock has to be ensured.

In principle, it would make more sense to prevent the C2 (or M0) from automatically going into low power mode. With other wireless stacks such as the stm32wb5x_Mac_802_15_4_fw.bin it does not do this either. The questions are:

• Why does this happen with the stm32wb5x_Phy_802_15_4_fw.bin?
• Or how can I prevent this?
• Or how can Zephyr prevent the clock switch or adjust the BRR register of the LPUART so that no garbage is printed out?

We are using:

• Zephyr v3.6.0
• on Win10
• Zephyr SDK 0.16.1

If anything is unclear, information is missing (for sure) and you need more info, please let me know and please be gracious to me. It's my first post (discussion) on Github ;)

Thanks in advance!

[erwango]

@asm5878 ^^