GPIO Interrupt in DSP IMX8MP

[mbahmani90]

Hi,

Hope you are all well

I would like to enable interrupt for a gpio pin in DSP IMX8MP.

I use GPIO5_8 and when I configure this pin as output it works well. However, when I configure the pin as an external interrupt input it doesn't work and the callback function is not invoked.

code:

#define LED0_NODE DT_ALIAS(led0)

/*
 * A build error on this line means your board is unsupported.
 * See the sample documentation for information on how to fix this.
 */
static const struct gpio_dt_spec test_gpio = GPIO_DT_SPEC_GET(LED0_NODE, gpios);

static struct gpio_callback gpio_cb_data;

void gpio_cb_fun(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
	printk("Interrupt!");
}

int main(void)
{
	printk("D: %s   T: %s \r\n" , __DATE__  , __TIME__);
	int ret;

	if (!gpio_is_ready_dt(&test_gpio)) {
		printk("GPIO not ready!\r\n");
		return 0;
	}else{
		printk("GPIO ready!\r\n");
	}

	ret = gpio_pin_configure_dt(&test_gpio, GPIO_INPUT);
	if (ret != 0) {
		printk("Error %d: failed to configure %s pin %d\n",
		       ret, test_gpio.port->name, test_gpio.pin);
		return 0;
	}

	ret = gpio_pin_interrupt_configure_dt(&test_gpio, GPIO_INT_EDGE_TO_ACTIVE);
	if (ret != 0) {
		printk("Error %d: failed to configure interrupt on %s pin %d\n",
			ret, test_gpio.port->name, test_gpio.pin);
		return 0;
	}	
	
	gpio_init_callback(&gpio_cb_data, gpio_cb_fun, BIT(test_gpio.pin));
	gpio_add_callback(test_gpio.port, &gpio_cb_data);
	
	// ret = gpio_pin_configure_dt(&test_gpio, GPIO_OUTPUT_ACTIVE);
	// if (ret < 0) {
	// 	return 0;
	// }

	printk("Start\r\n");
	while (1) {
		k_msleep(SLEEP_TIME_MS);
	}
	return 0;
}

device tree:

gpio5: gpio@30240000 {
	compatible = "nxp,imx-gpio";
	reg = <0x30240000 DT_SIZE_K(64)>;
	rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					     RDC_DOMAIN_PERM_RW)|\
			     RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
					     RDC_DOMAIN_PERM_RW))>;
	interrupt-parent = <&master2>;
	interrupts = <8>;						       
	gpio-controller;
	#gpio-cells = <2>;
	status = "okay";

};

dsp device tree:

/ {
	model = "NXP i.MX 8MPLUS Audio DSP";
	compatible = "nxp";

	aliases {
		led0 = &myled0;
	};

	leds {
		compatible = "gpio-keys";
		myled0: led_0 {
			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
				};
		status = "okay";
	};

	chosen {
		zephyr,sram = &sram0;
		zephyr,console = &uart4;
		zephyr,shell-uart = &uart4;
	};
};

&gpio5 {
	status = "okay";
};

Could you please explain if any thing else is required to do?

Thanks

[dbaluta]

adding @LaurentiuM1234 he should be able to help with the interrupts. The interrupts can be tricky because of the irqsteer.

[mbahmani90]

I have also checked
irqsteer RDC register = 0xFF
Master Interrupt Disable Register = 0x00

root@imx8mp-lpddr4-evk:~# devmem2 0x303D0520
/dev/mem opened.
Memory mapped at address 0xffffadd04000.
Read at address  0x303D0520 (0xffffadd04520): 0x000000FF
root@imx8mp-lpddr4-evk:~# devmem2 0x32FC2000
/dev/mem opened.
Memory mapped at address 0xffff90a59000.
Read at address  0x32FC2000 (0xffff90a59000): 0x00000000

[iuliana-prodan]

@mbahmani90 the address 0x32FC2000 is for irq_steer HDMI.
For DSP you need to use "irq_steer_audio_processor base address: 30A8_0000h":
See from RM (here):

[mbahmani90]

Thank for your response. You are right. However, As you see I didn't use memory map in the code. I only read the register's value in command line.

I also check the value of irq_steer_audio_processor:

root@imx8mp-lpddr4-evk:~# devmem2 0x303D0520
/dev/mem opened.
Memory mapped at address 0xffff92def000.
Read at address  0x303D0520 (0xffff92def520): 0x000000FF
root@imx8mp-lpddr4-evk:~# devmem2 0x30A80000
/dev/mem opened.
Memory mapped at address 0xffffbb472000.
Read at address  0x30A80000 (0xffffbb472000): 0x00000000

[mbahmani90]

As you can see in the device tree the IRQ_STEER memory address is 0x30a80000:

	soc {
	
		irqsteer: interrupt-controller@30a80000 {
			compatible = "nxp,irqsteer-intc";
			reg = <0x30a80000 DT_SIZE_K(64)>;

			#size-cells = <0>;
			#address-cells = <1>;

			master0: interrupt-controller@0 {
				compatible = "nxp,irqsteer-master";
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts-extended = <&clic 19 0 0>;
			};

			master1: interrupt-controller@1 {
				compatible = "nxp,irqsteer-master";
				reg = <1>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts-extended = <&clic 20 0 0>;
			};

			master2: interrupt-controller@2 {
				compatible = "nxp,irqsteer-master";
				reg = <2>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts-extended = <&clic 21 0 0>;
			};
		};
	
		ccm: ccm@30380000 {
			compatible = "nxp,imx-ccm";
			reg = <0x30380000 DT_SIZE_K(64)>;
			#clock-cells = <3>;
		};

		iomuxc: iomuxc@30330000 {
			compatible = "nxp,imx-iomuxc";
			reg = <0x30330000 DT_SIZE_K(64)>;
			status = "okay";
			pinctrl: pinctrl {
				status = "okay";
				compatible = "nxp,imx8mp-pinctrl";
			};
		};

		gpio3: gpio@30220000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30220000 DT_SIZE_K(64)>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			interrupt-parent = <&master2>;
			interrupts = <4>;					       
			gpio-controller;
			#gpio-cells = <2>;
			status = "okay";
		};
		
		gpio5: gpio@30240000 {
			compatible = "nxp,imx-gpio";
			reg = <0x30240000 DT_SIZE_K(64)>;
			rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW)|\
			       RDC_DOMAIN_PERM(M7_DOMAIN_ID,\
					       RDC_DOMAIN_PERM_RW))>;
			interrupt-parent = <&master2>;
			interrupts = <8>;						       
			gpio-controller;
			#gpio-cells = <2>;
			status = "okay";
		};
		
		ecspi2: spi@30830000 {
			compatible = "nxp,imx-ecspi";
			reg = <0x30830000 DT_SIZE_K(64)>;
			cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&master1>;
			interrupts = <0>;
			clocks = <&ccm IMX_CCM_ECSPI2_CLK 0 0>;
			status = "okay";
			a: spi-dev-a@0 {
				reg = <0>;
			};
		};

		lpi2c3: i2c@30a40000 {
			compatible = "nxp,imx-lpi2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x30a40000 0x10000>;
			interrupt-parent = <&master1>;
			interrupts = <5>;
			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
			status = "okay";
		};

		/*
		 * For now only UART4 is supported and
		 * tested with the serial driver
		 */
		uart4: uart@30a60000 {
			compatible = "nxp,imx-iuart";
			reg = <0x30a60000 0x10000>;
			/* TODO: This INTID is just a dummy
			 * until we can support UART interrupts
			 */
			interrupt-parent = <&master0>;
			interrupts = <29 0 0>;
			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
			status = "disabled";
		};

		mailbox0: mailbox@30e70000 {
			compatible = "nxp,imx-mu";
			reg = <0x30e70000 0x10000>;
			interrupt-parent = <&clic>;
			interrupts = <7 0 0>;
			rdc = <0>;
			status = "disabled";
		};
	};

[iuliana-prodan]

@mbahmani90 ok, that's good.
So the problem is that the GPIO5 cannot be set as external interrupt?

[mbahmani90]

How did you find out? Could you please explain which of the gpios are usable for IRQ_STEER?

[iuliana-prodan]

How did you find out?

Find out what?
I've asked you "the problem is that the GPIO5 cannot be set as external interrupt" to be sure if I understand correctly what you are asking?
I'm not sure what is not working here?

From IMX8MP reference manual, in Chapter 7 Interrupts and DMA I see that GPIOs can be interrupt sources for Cortex A53 (Table 7-1) and for Cortex M7 (table 7-2).
Interrupt number is 72 for signals 0 - 15 and 73 for signals 16 - 32:

So

gpio5: gpio@30240000 {
...
interrupt-parent = <&master2>;
interrupts = <8>;

is ok, be sure to have signals 0-15, otherwise will be interrupts = <9>; for signals 16 - 32.

Also, can you please check the values for Channel n Interrupt Status Register (CHn_STATUS0 -CHn_STATUS4), to see if the interrupt is set or not:

[mbahmani90]

Sorry I didn't understand you question. Yes, the problem is that GPIO5 external interrupt doesn't work.

I am using GPIO5_8. Therefore it should be "interrupts = <8>;".

I have already checked the IRQ_STEER registers and the values are all zero

root@imx8mp-lpddr4-evk:~# devmem2 0x30A8002C
/dev/mem opened.
Memory mapped at address 0xffff9c402000.
Read at address  0x30A8002C (0xffff9c40202c): 0x00000000
root@imx8mp-lpddr4-evk:~# devmem2 0x30A80030
/dev/mem opened.
Memory mapped at address 0xffffa356e000.
Read at address  0x30A80030 (0xffffa356e030): 0x00000000
root@imx8mp-lpddr4-evk:~# devmem2 0x30A80034
/dev/mem opened.
Memory mapped at address 0xffff8cabd000.
Read at address  0x30A80034 (0xffff8cabd034): 0x00000000
root@imx8mp-lpddr4-evk:~# devmem2 0x30A80038
/dev/mem opened.
Memory mapped at address 0xffff93235000.
Read at address  0x30A80038 (0xffff93235038): 0x00000000
root@imx8mp-lpddr4-evk:~# devmem2 0x30A8003C
/dev/mem opened.
Memory mapped at address 0xffff9b349000.
Read at address  0x30A8003C (0xffff9b34903c): 0x00000000

Furthermore, the GPIO5_8 interrupt is enable and configured to failing edge:

root@imx8mp-lpddr4-evk:~# devmem2 0x30240014
/dev/mem opened.
Memory mapped at address 0xffff98804000.
Read at address  0x30240014 (0xffff98804014): 0x00000100
root@imx8mp-lpddr4-evk:~# devmem2 0x3024000C
/dev/mem opened.
Memory mapped at address 0xffff9ca23000.
Read at address  0x3024000C (0xffff9ca2300c): 0x00030000

It seems that Mask Register should be set to one:

root@imx8mp-lpddr4-evk:~# devmem2 0x30A8000C w 0x00000100
/dev/mem opened.
Memory mapped at address 0xffff95e1a000.
Read at address  0x30A8000C (0xffff95e1a00c): 0x00000000
Write at address 0x30A8000C (0xffff95e1a00c): 0x00000100, readback 0x00000100

But now when the interrupt occurs, I receive the following error in DSP side.

[00:00:12.488,000] <err> os:  ** Spurious INTERRUPT(s) 0x100008, INTENABLE = 0x380114
[00:00:12.488,000] <err> os: >>> ZEPHYR FATAL ERROR 1: Unhandled interrupt on CPU 0
[00:00:12.488,000] <err> os: Current thread: 0x9240abf8 (unknown)
[00:00:12.512,000] <err> os: Halting system

[mbahmani90]

I tested with GPIO3_20, (IRQ 69 - master2_5) and when the interrupt occur I got the same error:

[00:00:19.954,000] <err> os:  ** Spurious INTERRUPT(s) 0x100008, INTENABLE = 0x380124
[00:00:19.954,000] <err> os: >>> ZEPHYR FATAL ERROR 1: Unhandled interrupt on CPU 0
[00:00:19.954,000] <err> os: Current thread: 0x9240abf8 (unknown)
[00:00:19.977,000] <err> os: Halting system

I also disabled the interrupt callback but again the error occurs.

// gpio_init_callback(&gpio_cb_data, gpio_cb_fun, BIT(test_gpio.pin));
// gpio_add_callback(test_gpio.port, &gpio_cb_data);

[LaurentiuM1234]

Hey, @mbahmani90!

Would you mind also attaching the output of gen_isr_tables.py? The command for this would look like:

west build -p -b imx8qxp_mek//adsp samples/hello_world/ -- -DGEN_ISR_TABLE_EXTRA_ARG=-d

(replace the board and sample with your own)

EDIT:
Also, could you please:

1. Try switching the interrupt parent of your gpio5 node from master2 to master1? In this case, are you getting the same spurious interrupt error you've mentioned?
2. Attach the values of all the CHn_MASK registers before the interrupt parent change and after it?

[mbahmani90]

It seems that I IMX_GPIO is enabled.

I don't find any MCUX GPIO option.

[mbahmani90]

I found IRQ_CONNECT and irq_enable in gpio_imx.c

		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq),		\
			    DT_INST_IRQ_BY_IDX(n, 0, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq));		\
									\
		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq),		\
			    DT_INST_IRQ_BY_IDX(n, 1, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq));		\

Should I change both similar to gpio_mcux_igpio.c?

[LaurentiuM1234]

Yes, please. Don't forget about the calls in irq_enable as well.

[mbahmani90]

I'll do it after lunch!
Thanks.

[mbahmani90]

The gpio_imx.c modification:

		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, 0, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\
									\
		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, 1, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\

gen_isr_tables.py

gen_isr_tables.py: Level    Bits        Bitmask
gen_isr_tables.py: ----------------------------
gen_isr_tables.py:     1       8     0x000000FF
gen_isr_tables.py:     2       8     0x0000FF00
gen_isr_tables.py:     3       8     0x00FF0000
gen_isr_tables.py: 2nd level offsets: [19, 20, 21]
gen_isr_tables.py: Found intlist section: ".intList"
gen_isr_tables.py: (224, 0)
gen_isr_tables.py: Configured interrupt routing
gen_isr_tables.py: handler    irq flags param
gen_isr_tables.py: --------------------------
gen_isr_tables.py: 0x92403a30 21  0     0x924092a4
gen_isr_tables.py: 0x92403a30 20  0     0x92409298
gen_isr_tables.py: 0x92403a30 19  0     0x9240928c
gen_isr_tables.py: 0x92406bec 40  0     0x924075dc
gen_isr_tables.py: 0x92406bec 37  0     0x924075f0
gen_isr_tables.py: 0x92403fac 276 0     0x92407604
gen_isr_tables.py: 0x92404524 2   0     0x0
gen_isr_tables.py: offset is 0
gen_isr_tables.py: num_vectors is 224
gen_isr_tables.py: IRQ = 0x15
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 21
gen_isr_tables.py: IRQ_Pos  = 21
gen_isr_tables.py: IRQ = 0x14
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 20
gen_isr_tables.py: IRQ_Pos  = 20
gen_isr_tables.py: IRQ = 0x13
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 19
gen_isr_tables.py: IRQ_Pos  = 19
gen_isr_tables.py: IRQ = 0x28
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 40
gen_isr_tables.py: IRQ_Pos  = 40
gen_isr_tables.py: IRQ = 0x25
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 37
gen_isr_tables.py: IRQ_Pos  = 37
gen_isr_tables.py: IRQ = 0x114
gen_isr_tables.py: IRQ_level = 2
gen_isr_tables.py: IRQ_Indx = 1
gen_isr_tables.py: IRQ_Pos  = 96
gen_isr_tables.py: IRQ = 0x2
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 2
gen_isr_tables.py: IRQ_Pos  = 2
gen_isr_tables.py: Chosen parser does not support vector table linker file
gen_isr_tables.py: Chosen parser does not support software interrupt linker file

Mask registers for master1_40 and master 2_8:

Master1 Masks -> 0: 0  1: 0  2: 0  3: 0x1  4: 0
Master2 Masks -> 0: 0  1: 0  2: 0  3: 0x1  4: 0

[mbahmani90]

I will test it tomorrow.
Thanks

[LaurentiuM1234]

The gpio_imx.c modification:

		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, 0, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\
									\
		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, 1, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\

gen_isr_tables.py

gen_isr_tables.py: Level    Bits        Bitmask
gen_isr_tables.py: ----------------------------
gen_isr_tables.py:     1       8     0x000000FF
gen_isr_tables.py:     2       8     0x0000FF00
gen_isr_tables.py:     3       8     0x00FF0000
gen_isr_tables.py: 2nd level offsets: [19, 20, 21]
gen_isr_tables.py: Found intlist section: ".intList"
gen_isr_tables.py: (224, 0)
gen_isr_tables.py: Configured interrupt routing
gen_isr_tables.py: handler    irq flags param
gen_isr_tables.py: --------------------------
gen_isr_tables.py: 0x92403a30 21  0     0x924092a4
gen_isr_tables.py: 0x92403a30 20  0     0x92409298
gen_isr_tables.py: 0x92403a30 19  0     0x9240928c
gen_isr_tables.py: 0x92406bec 40  0     0x924075dc
gen_isr_tables.py: 0x92406bec 37  0     0x924075f0
gen_isr_tables.py: 0x92403fac 276 0     0x92407604
gen_isr_tables.py: 0x92404524 2   0     0x0
gen_isr_tables.py: offset is 0
gen_isr_tables.py: num_vectors is 224
gen_isr_tables.py: IRQ = 0x15
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 21
gen_isr_tables.py: IRQ_Pos  = 21
gen_isr_tables.py: IRQ = 0x14
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 20
gen_isr_tables.py: IRQ_Pos  = 20
gen_isr_tables.py: IRQ = 0x13
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 19
gen_isr_tables.py: IRQ_Pos  = 19
gen_isr_tables.py: IRQ = 0x28
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 40
gen_isr_tables.py: IRQ_Pos  = 40
gen_isr_tables.py: IRQ = 0x25
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 37
gen_isr_tables.py: IRQ_Pos  = 37
gen_isr_tables.py: IRQ = 0x114
gen_isr_tables.py: IRQ_level = 2
gen_isr_tables.py: IRQ_Indx = 1
gen_isr_tables.py: IRQ_Pos  = 96
gen_isr_tables.py: IRQ = 0x2
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 2
gen_isr_tables.py: IRQ_Pos  = 2
gen_isr_tables.py: Chosen parser does not support vector table linker file
gen_isr_tables.py: Chosen parser does not support software interrupt linker file

Mask registers for master1_40 and master 2_8:

Master1 Masks -> 0: 0  1: 0  2: 0  3: 0x1  4: 0
Master2 Masks -> 0: 0  1: 0  2: 0  3: 0x1  4: 0

Interesting, I wonder why this works. I was expecting the build to fail since as far as I can tell the variable i you've used isn't defined anywhere? Are you sure you're using gpio_imx.c? If so, you need to modify:

DT_INST_IRQ_BY_IDX(n, 0, irq) to DT_INST_IRQN_BY_IDX(n, 0)

and

DT_INST_IRQ_BY_IDX(n, 1, irq) to DT_INST_IRQN_BY_IDX(n, 1)

[mbahmani90]

As you can see in the previous message I have changed it!

                IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, 0, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\
									\
		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, 1, priority),		\
			    imx_gpio_port_isr,				\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\

[mbahmani90]

You are right it seems that there is nothing to do with gpio_imx.c file. I created a syntax error in gpio_imx.c but I didn't receive any error in build.

[mbahmani90]

let me change gpio_xtensa.c

[mbahmani90]

It seems that gpio_xtensa.c has not been used.

[mbahmani90]

Hi,
Hope you are fine!

I logged the functions in gpio_mcux_igpio.c and I made assured this driver is called with no issue.

Then I changed gpio_mcux_igpio.c based on your suggestion but I still receive the Spurious INTERRUPT error:

#define MCUX_IGPIO_IRQ_INIT(n, i)					\
	do {								\
		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i),		\
			    DT_INST_IRQ_BY_IDX(n, i, priority),		\
			    mcux_igpio_port_isr,			\
			    DEVICE_DT_INST_GET(n), 0);			\
									\
		irq_enable(DT_INST_IRQN_BY_IDX(n, i));		\
	} while (false)

Thanks

[LaurentiuM1234]

Hi,

Could you please attach the output of gen_isr_tables.py?

Also, did you manually write any of the CHn_MASK registers before doing the dump?

Btw, which interrupt ID and parent are you using for GPIO5 in this scenario?

[mbahmani90]

Hi,

I used GPIO5_8. I set CHn_MASK registers both manually and default.
I will send the other information as soon as possible.

Thanks.

[mbahmani90]

gen_isr_tables.py

gen_isr_tables.py: Level    Bits        Bitmask
gen_isr_tables.py: ----------------------------
gen_isr_tables.py:     1       8     0x000000FF
gen_isr_tables.py:     2       8     0x0000FF00
gen_isr_tables.py:     3       8     0x00FF0000
gen_isr_tables.py: 2nd level offsets: [19, 20, 21]
gen_isr_tables.py: Found intlist section: ".intList"
gen_isr_tables.py: (224, 0)
gen_isr_tables.py: Configured interrupt routing
gen_isr_tables.py: handler    irq flags param
gen_isr_tables.py: --------------------------
gen_isr_tables.py: 0x92403b5c 21  0     0x92409484
gen_isr_tables.py: 0x92403b5c 20  0     0x92409478
gen_isr_tables.py: 0x92403b5c 19  0     0x9240946c
gen_isr_tables.py: 0x924041b8 10516 0     0x924077b0
gen_isr_tables.py: 0x924041b8 9748 0     0x924077c4
gen_isr_tables.py: 0x92404388 276 0     0x924077d8
gen_isr_tables.py: 0x92404900 2   0     0x0
gen_isr_tables.py: offset is 0
gen_isr_tables.py: num_vectors is 224
gen_isr_tables.py: IRQ = 0x15
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 21
gen_isr_tables.py: IRQ_Pos  = 21
gen_isr_tables.py: IRQ = 0x14
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 20
gen_isr_tables.py: IRQ_Pos  = 20
gen_isr_tables.py: IRQ = 0x13
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 19
gen_isr_tables.py: IRQ_Pos  = 19
gen_isr_tables.py: IRQ = 0x2914
gen_isr_tables.py: IRQ_level = 2
gen_isr_tables.py: IRQ_Indx = 41
gen_isr_tables.py: IRQ_Pos  = 136
gen_isr_tables.py: IRQ = 0x2614
gen_isr_tables.py: IRQ_level = 2
gen_isr_tables.py: IRQ_Indx = 38
gen_isr_tables.py: IRQ_Pos  = 133
gen_isr_tables.py: IRQ = 0x114
gen_isr_tables.py: IRQ_level = 2
gen_isr_tables.py: IRQ_Indx = 1
gen_isr_tables.py: IRQ_Pos  = 96
gen_isr_tables.py: IRQ = 0x2
gen_isr_tables.py: IRQ_level = 1
gen_isr_tables.py: IRQ_Indx = 2
gen_isr_tables.py: IRQ_Pos  = 2
gen_isr_tables.py: Chosen parser does not support vector table linker file
gen_isr_tables.py: Chosen parser does not support software interrupt linker file

[mbahmani90]

I will send other information soon.
Thanks.

[mbahmani90]

Master1:

interrupt-parent = <&master1>;
interrupts = <40>;
Master1 Masks -> 0: 0  1: 0  2: 0x120  3: 0x1  4: 0   // Error Spurious INTERRUPT

Master2:

interrupt-parent = <&master2>;
interrupts = <8>;

Master2 Masks -> 0: 0  1: 0x120  2: 0  3: 0x1  4: 0   // No Error

[mbahmani90]

The problem was solved but I don't know how to clean the code.

I tracked the code and I found that the error is coming from "irqsteer_isr_dispatcher" in "intc_nxp_irqsteer.c". then I logged the code and I found that "_sw_isr_table[table_idx].isr" has not been initialized. I defined a function ( test_isr ) and used "z_isr_install" to temporary initialized "_sw_isr_table[table_idx].isr" . However, it is hard coded. I would really appreciate it if you could help me in this regard.

void test_isr(const void *pvParam){
	int x = (int) pvParam;
	printf("XX: %x \r\n" , x);
	return ;
}

static void irqsteer_isr_dispatcher(const void *data)
{
	struct irqsteer_dispatcher *dispatcher;
	const struct irqsteer_config *cfg;
	uint32_t table_idx;
	int system_irq, zephyr_irq, i;
	uint64_t status;
	void *temp_arg1 = (void *) 1;

	dispatcher = (struct irqsteer_dispatcher *)data;
	cfg = dispatcher->dev->config;

	/* fetch master interrupts status */
	status = IRQSTEER_GetMasterInterruptsStatus(UINT_TO_IRQSTEER(cfg->regmap_phys),
						    dispatcher->master_index);
	printf("irqsteer_isr_dispatcher : %lld , IRQ_TABLE_SIZE= %d\r\n" , status, IRQ_TABLE_SIZE );
	for (i = 0; status; i++) {
		/* if bit 0 is set then that means relative INTID i is asserted */
		if (status & 1) {
			/* convert master-relative INTID to a system INTID */
			printf("to_system_irq\r\n");
			system_irq = to_system_irq(cfg->regmap_phys, i,
						   dispatcher->master_index);
			/* convert system INTID to a Zephyr INTID */
			zephyr_irq = to_zephyr_irq(cfg->regmap_phys, system_irq, dispatcher);
			printf("zephyr_irq : %x\r\n" , zephyr_irq);
			/* compute index in the SW ISR table */
			table_idx = z_get_sw_isr_table_idx(zephyr_irq);
			printf("table_idx : %x\r\n" , table_idx);
			z_isr_install(table_idx, test_isr, temp_arg1);
			/* call child's ISR */
			_sw_isr_table[table_idx].isr(_sw_isr_table[table_idx].arg);
		}
		status >>= 1;
	}
}

The output:

[LaurentiuM1234]

In intc_nxp_irqsteer.c, if I write:

if(table_idx == 0x68){
	z_isr_install(table_idx, test_isr, temp_arg1);
}

instead of:

z_isr_install(table_idx, test_isr, temp_arg1);

Be careful here as z_isr_install() doesn't take an ISR table index. Instead, it takes a "zephyr" INTID as its argument. What ends up happening here is in this case:

if(table_idx == 0x68){
	z_isr_install(table_idx, test_isr, temp_arg1);
}

you're overwriting the ISR for an interrupt which I'm assuming you're not using (i.e: system interrupt 40) so your gpio callback function should still be called in this case (which seems to be the cause of the issue?). You should be able to test this out by replacing 0x68 with 0x2914 or by printing something in your GPIO callback.

void gpio_cb_fun(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{

long unsigned int *gpio_setdataout_addr = ((long unsigned int *) 0x30240000);
long unsigned int *gpio_direction_addr = ((long unsigned int *) 0x30240004);

*gpio_direction_addr = 0x000FC220;

*gpio_setdataout_addr ^= (1 << 9);
printf("XX\r\n");
return ;
}

Have you tried doing nothing in your gpio_cb_fun() (i.e: just do a return statement)? If this works (i.e: no Linux errors) then this might not be an interrupt-related issue.

[mbahmani90]

You should be able to test this out by replacing 0x68 with 0x2914

You are right, now it works well. What I have found is that if the interrupt mask register is enable and no callback function was defined, after interrupt occurs the Linux would stop working and freeze. (I only test for GPIO5_8 and maybe it is not correct for other interrupts.)

Only one question remains how did you know for IRQ 72 I should use 0x2914? Is there any table or calculation?

Thanks for your help!

[LaurentiuM1234]

You are right, now it works well. What I have found is that if the interrupt mask register is enable and no callback function was defined, after interrupt occurs the Linux would stop working and freeze. (I only test for GPIO5_8 and maybe it is not correct for other interrupts.)

You mean the IRQ_STEER driver works okay for you without modifying it now?

Only one question remains how did you know for IRQ 72 I should use 0x2914? Is there any table or calculation?

We do have some sort of table in the documentation from intc_nxp_irqsteer.c and there's also https://docs.zephyrproject.org/latest/kernel/services/interrupts.html which explains the multi-level interrupt stuff.

Basically the theory is as follows:

On i.MX8MP we have 160 system interrupts (0-159). First 32 interrupts are signaled to the DSP via DSP interrupt line 19, next 64 interrupts are signaled via DSP interrupt line 20 and last 64 interrupts are signaled via DSP interrupt line 21. When you configure the DTS you need to use a master-relative interrupt ID. A master is basically a DSP interrupt line (here: 19, 20, and 21). To find out which master your interrupt belongs to you can use the following table:

[0:31] => master0 (interrupts from 0 to 31 are signaled to the DSP via master 0 (interrupt line 19))
[32:95] => master1 (interrupts from 32 to 95 are signaled to the DSP via master 1 (interrupt line 20))
[96:159] => master2 (interrupts from 96 to 159 are signaled to the DSP via master 2 (interrupt line 21))

So in your case interrupt 72 would belong to master1 (since it's in range 32 - 95). After you find this out, you need to decrement the base of the master. Here. the base would be 32 because master1 interrupts start at 32. As such, in your DTS interrupt 72 would have the ID 40 and parent master1.

To encode it to a multi-level interrupt ID you need to: +1 your interrupt, left shift the interrupt by 8 and do a bitwise OR with the master interrupt (here it would be 20). As such, you'll end up having: (((40 + 1) << 8) | 0x14) which is 0x2914.

I strongly recommend you read the documentation from intc_nxp_irqsteer.c as it should explain this a bit more clearly. Feedback on it would be much appreciated!

[mbahmani90]

I have replaced 0x68 with 0x2914 and it works fine.

z_isr_install(0x2914, test_isr, temp_arg1);

Bytheway I use z_isr_install in the main function not in the irqsteer_isr_dispatcher

Sorry I should do something else now I don't have access the code now. I will send you the code soon.

Thanks.

[mbahmani90]

in main.c

void test_isr(const void *pvParam){

	int x = (int) pvParam;
	*gpio_setdataout_addr1 ^= (1 << 9);	
	printf("XX: %x \r\n" , x);
	return ;
}


int main(void)
{
	printk("D: %s   T: %s \r\n" , __DATE__  , __TIME__);
	int ret;
	bool led_state = true;
	void *temp_arg1 = (void *) 2;

	if (!gpio_is_ready_dt(&test_gpio)) {
		printk("GPIO not ready!\r\n");
		return 0;
	}else{
		printk("GPIO ready!\r\n");
	}

	ret = gpio_pin_configure_dt(&test_gpio, GPIO_INPUT);
	if (ret != 0) {
		printk("Error %d: failed to configure %s pin %d\n",
		       ret, test_gpio.port->name, test_gpio.pin);
		return 0;
	}

	ret = gpio_pin_interrupt_configure_dt(&test_gpio, GPIO_INT_EDGE_TO_INACTIVE);
	if (ret != 0) {
		printk("Error %d: failed to configure interrupt on %s pin %d\n",
			ret, test_gpio.port->name, test_gpio.pin);
		return 0;
	}	

	*gpio_direction_addr1 = 0x000FC220;

	*gpio5_8_iomuxc1 = 0x00000005;
	*gpio5_9_iomuxc1 = 0x00000005;

    uint32_t *irq_steer_ch0_status0   = ((uint32_t *) 0x30A8002C);
	uint32_t *irq_steer_ch0_status1   = ((uint32_t *) 0x30A80030);
	uint32_t *irq_steer_ch0_status2   = ((uint32_t *) 0x30A80034);
	uint32_t *irq_steer_ch0_status3   = ((uint32_t *) 0x30A80038);
	uint32_t *irq_steer_ch0_status4   = ((uint32_t *) 0x30A8003C);

	uint32_t *ch0_mask0 = ((uint32_t *) 0x30A80004);
	uint32_t *ch0_mask1 = ((uint32_t *) 0x30A80008);
	uint32_t *ch0_mask2 = ((uint32_t *) 0x30A8000C);
	uint32_t *ch0_mask3 = ((uint32_t *) 0x30A80010);
	uint32_t *ch0_mask4 = ((uint32_t *) 0x30A80014);

	*ch0_mask0 = 0;
	*ch0_mask1 = 0;
	*ch0_mask2 = (1 << 8); // 5
	*ch0_mask3 = 0;
	*ch0_mask4 = 0; 

	//gpio_init_callback(&gpio_cb_data, gpio_cb_fun, BIT(test_gpio.pin));
	//gpio_add_callback(test_gpio.port, &gpio_cb_data);
	
	z_isr_install(0x2914, test_isr, temp_arg1);
	
	printk("Start %d\r\n" , test_gpio.pin);
	while (1) {

		printf("Master2 Masks -> 0: %#x  1: %#x  2: %#x  3: %#x  4: %#x \r\n" , *ch0_mask0 , *ch0_mask1, *ch0_mask2, *ch0_mask3, *ch0_mask4);
		

		k_msleep(SLEEP_TIME_MS);
	}
	return 0;
}

intc_nxp_irqsteer.c is default.

static void irqsteer_isr_dispatcher(const void *data)
{
	struct irqsteer_dispatcher *dispatcher;
	const struct irqsteer_config *cfg;
	uint32_t table_idx;
	int system_irq, zephyr_irq, i;
	uint64_t status;

	dispatcher = (struct irqsteer_dispatcher *)data;
	cfg = dispatcher->dev->config;

	/* fetch master interrupts status */
	status = IRQSTEER_GetMasterInterruptsStatus(UINT_TO_IRQSTEER(cfg->regmap_phys),
						    dispatcher->master_index);
	
	for (i = 0; status; i++) {
		/* if bit 0 is set then that means relative INTID i is asserted */
		if (status & 1) {
			/* convert master-relative INTID to a system INTID */
			system_irq = to_system_irq(cfg->regmap_phys, i,
						   dispatcher->master_index);

			/* convert system INTID to a Zephyr INTID */
			zephyr_irq = to_zephyr_irq(cfg->regmap_phys, system_irq, dispatcher);
			/* compute index in the SW ISR table */
			table_idx = z_get_sw_isr_table_idx(zephyr_irq);
			
			/* call child's ISR */
			_sw_isr_table[table_idx].isr(_sw_isr_table[table_idx].arg);
		}

		status >>= 1;
	}
}