Ethernet Driver for Intel Agilex 7 socfpga

[sanjatpanigrahi]

Hi All,
I am trying to implement an Ethernet Driver on the Intel Agilex 7 FPGA which has an arm a53 MPU.

I am bit confused with respect to the HPS register bit name and the macros define in the file include/zephyr/dt-bindings/reset/intel_socfpga_reset.h

Can someone clarify the below:

As per Zephyr RTOS, the Reset Line Value is calculated as below (an example):

Deriving Reset Line value

per0modrst register offset = 0x24;

NAND RSTLINE pin = 5;

RSTMGR_NAND_RSTLINE = (0x24 * 8) + 5 = 293

Using the above method if, I calculate the reset line value for EMAC0:

Reset Line Value for EMAC0 = (0x24 * 0x08) + 0x00 = 0x120 = 288 (in decimal)
In the Zephyr RTOS include/zephyr/dt-bindings/reset/intel_socfpga_reset.h we have:
#define RSTMGR_TSN0_RSTLINE 288
Does anybody knows that EMAC can also be termed/called as TSN?
Does TSN => Time Sensitive Network?
Can we correlate EMAC with TSN?

The below is the Peripheral 0 Module Register:

4.5.3.3 Ethernet with GenAVB/TSN stack
A more complex Ethernet use case uses the GenAVB/TSN Stack, which provides advanced implementation for AVB as well as Time-Sensitive Networking (TSN) functionalities. Some functions for the latter do require special TSN hardware support, available in the i.MX 8M Plus SoC for instance.

Is it possible that EMAC is also termed as TSN (Time Sensitive Network)?
Couldn’t find anything specific on Zephyr website 😞

Best Regards,
Sanjat