Whether ESP32 supports W25Q256

[sam131208]

Is your enhancement proposal related to a problem? Please describe.
I got some information on the esp32 forum , “Starting with ESP-IDF 4.4, 32-bit addressing was added for a few specific flash models (W25Q256, GD25Q256, and one MXIC part).”
But, when I use spi_flash_get_chip_size() to get fllash size, it returns 16MB. Is the latest zephyr version not yet supported w25q256?

Describe the solution you'd like
Use spi_flash_get_chip_size() to get the correct flash size ， and can be read or write the whole flash.

[nordicjm]

There is a template when create an enhancement request which you should fill in, not completely delete, can you edit your issue, add it back in and fill it in?

[rftafas]

Are you building a custom board with ESP32 down to chip level? Which chip?

[sam131208]

Are you building a custom board with ESP32 down to chip level? Which chip?

The chip I use is ESP32-D0WD-V3, chip version 3. W25Q256 The front 16MB is accessible.

[rftafas]

Although flash is supported, according to TRM pg. 24, SPI flash size max is 16MB.

[sam131208]

Although flash is supported, according to TRM pg. 24, SPI flash size max is 16MB.

You mean that you can't use the next 16MB as a file system？I thought it could be accessed by SPI0.

[rftafas]

Hi!

Did you mean SPI1? SPI0 is the normal SPI flash controller that goes through cache and cap is 16MB.

Ptal:

https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/spi_flash/index.html

This means you may need to test Zephyr APIs along SPI1 to check if they can behave like esp_flash_* for the upper flash half.