multiple imx-flexspi-nor flash ICs #57483

ShahinHaque97-CT · 2023-05-02T13:40:44Z

ShahinHaque97-CT
May 2, 2023

Hello,

I am working with the NXP RT1040. I have two flash ICs specifically is25wp064, one is used for the main flash for the NXP MCU and the second will be used for littlefs.

Here is my dtsi
pinmux_flash: pinmux_flexspi1 { group0 { pinmux = <&iomuxc_gpio_sd_b1_05_flexspi_a_dqs>, <&iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b>, <&iomuxc_gpio_sd_b1_04_flexspi_a_ss1_b>, <&iomuxc_gpio_sd_b1_07_flexspi_a_sclk>, <&iomuxc_gpio_sd_b1_08_flexspi_a_data0>, <&iomuxc_gpio_sd_b1_09_flexspi_a_data1>, <&iomuxc_gpio_sd_b1_10_flexspi_a_data2>, <&iomuxc_gpio_sd_b1_11_flexspi_a_data3>; drive-strength = "r0-6"; slew-rate = "slow"; nxp,speed = "100-mhz"; }; };

Here is the DTS
`
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
pinctrl-0 = <&pinmux_flash>;
pinctrl-names = "default";
ahb-bufferable;
ahb-cacheable;
sck-differential-clock;
combination-mode;
rx-clock-source = <1>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
core_flash: is25wp064@0 {
compatible = "nxp,imx-flexspi-nor";
size = <67108864>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
erase-block-size = <4096>;
write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        boot_partition: partition@0 {
            label = "mcuboot";
            reg = <0x00000000 DT_SIZE_K(64)>;
        };
        slot0_partition: partition@10000 {
            label = "image-0";
            reg = <0x00010000 DT_SIZE_M(3)>;
        };
        slot1_partition: partition@310000 {
            label = "image-1";
            reg = <0x00310000 DT_SIZE_M(3)>;
        };
        scratch_partition: partition@610000 {
            label = "image-scratch";
            reg = <0x00610000 DT_SIZE_K(1984)>;
        };
    };
};
storage_flash: is25wp064@1 {
    compatible = "nxp,imx-flexspi-nor";
    size = <67108864>;
    reg = <1>;
    spi-max-frequency = <133000000>;
    status = "okay";
    jedec-id = [9d 70 17];
    erase-block-size = <4096>;
    write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;
        lfs_part: partition@0 {
            label = "storage";
            reg = <0x0000000 DT_SIZE_M(8)>;
        };
    };
};

};
`

Before I go into little fs, I have loaded the spi_flash example to do a basic read write operation and setting both devices show as being successful.

example edit:
const struct device *flash_dev = DEVICE_DT_GET(DT_NODELABEL(core_flash)); //const struct device *flash_dev = DEVICE_DT_GET(DT_NODELABEL(storage_flash));

I decided to verify this by putting a scope on the chip select lines and it shows that the same flash IC is being used and the second chip select isn't being selected.

How would I select the second IC? the second ic is already denoted as is25wp064@1 and reg = <1>;

Answered by DerekSnell

May 2, 2023

Hi @ShahinHaque97-Corintech ,

[Edited: this comment is out of date. The FlexSPI driver does support this now, see new comment below.]

Currently the Zephyr FlexSPI driver does not support having multiple memory devices on the same FlexSPI. See this PR comment.

If you are interested in adding this support, another discussion has details on the FlexSPI memory mapping with multiple chip selects. Best regards

View full answer

DerekSnell · 2023-05-02T14:08:52Z

DerekSnell
May 2, 2023
Collaborator

Hi @ShahinHaque97-Corintech ,

[Edited: this comment is out of date. The FlexSPI driver does support this now, see new comment below.]

Currently the Zephyr FlexSPI driver does not support having multiple memory devices on the same FlexSPI. See this PR comment.

If you are interested in adding this support, another discussion has details on the FlexSPI memory mapping with multiple chip selects. Best regards

4 replies

yunheQin Jan 26, 2024

Hi DerekSnell

lastly, I also encountered the similar issue using the mimxrt1062 to drive 2 QSPI flash which connect to two physical ports (FLEXSPIA1,FLEXSPIA2). And the write/read flash application comes from "Zephy/samples/driver/spi_flash". But the flash on FLEXSPIA2 could not read successfully? could you help me to have a look at this issue?
the select dts file as following shown:

&flexspi {
status = "okay";
pinctrl-0 = <&pinmux_flexspi1>;
pinctrl-names = "default";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(32)>;
mt25qu256: mt25qu256@0 {
compatible = "nxp,imx-flexspi-nor";
size = <33554432>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [20 bb 19];
erase-block-size = <4096>;
write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        boot_partition: partition@0 {
            label = "mcuboot";
            reg = <0x00000000 DT_SIZE_M(4)>;
        };
        slot0_partition: partition@400000 {
            label = "image-0";
            reg = <0x00400000 DT_SIZE_M(4)>;
        };
        slot1_partition: partition@800000 {
            label = "image-1";
            reg = <0x00800000 DT_SIZE_M(4)>;
        };
        scratch_partition: partition@B00000 {
            label = "image-scratch";
            reg = <0x00B00000 DT_SIZE_M(4)>;
        };
        storage_partition: partition@F00000 {
            label = "storage";
            reg = <0x00F00000 DT_SIZE_M(16)>;
        };
    };
};

};

&flexspi2 {
status = "okay";
pinctrl-0 = <&pinmux_flexspi2>;
pinctrl-names = "default";
ahb-prefetch;
ahb-read-addr-opt;
ahb-bufferable;
ahb-cacheable;
sck-differential-clock;
rx-buffer-config = <1 7 11 1024>;
rx-clock-source = <1>;
reg = <0x402a4000 0x3c00>, <0x70000000 DT_SIZE_M(32)>;
mt25qu256_fpga: mt25qu256_fpga@1 {
compatible = "nxp,imx-flexspi-nor-fpga";
size = <DT_SIZE_M(32*8)>;
reg = <1>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [20 bb 19];
erase-block-size = <4096>;
write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;
        fpga_storage_partition: partition@0 {
            label = "storage";
            reg = <0x00000000 DT_SIZE_M(32)>;
        };
    };
};

};

and the following image is the run test result through UART.

DerekSnell Jan 26, 2024
Collaborator

Hi @yunheQin ,
The Zephyr FlexSPI driver still does not yet support multiple memories on the same FlexSPI. To do so, you will need to configure the FlexSPI registers and LUT to support both devices.

NXP is working now to update this driver to support multiple memories. We plan to provide an example once it is functional. This will likely be in a couple weeks. This issue will be updated once that support is enabled. In the meantime if you need to enable this for your board, one option is to call the fsl_flexspi APIs from HAL and configure the FlexSPI as needed.

Best regards

ShahinHaque97-CT Mar 17, 2024
Author

@DerekSnell Do you have any update on this?

DerekSnell Mar 18, 2024
Collaborator

Hi @ShahinHaque97-CT ,
NXP is working on an example demonstrating multiple memories on a single FlexSPI. We are using the MIMXRT685-EVK board for this, because it has a QSPI flash and pSRAM on the same FlexSPI. However, that device cannot boot directly from the QSPI flash when the FlexSPI also enables the pSRAM. Therefore, our example will use MCUboot to enable the FlexSPI after the device has booted from QSPI.

But MCUboot requires an update to enable this use-case. We are working to merge this MCUboot PR, and then we can work on releasing the example.

Best regards

ShahinHaque97-CT · 2023-05-03T09:13:34Z

ShahinHaque97-CT
May 3, 2023
Author

I will reassign it to a different pin. Unfortunately, I have uart8_rx on the dqs pin for flexspi2, and the only alternative for uart8_rx is SEMC_DQS which needs to be floating. For now, I will reassign it to a regular lpspi

0 replies

DerekSnell · 2024-05-23T14:22:07Z

DerekSnell
May 23, 2024
Collaborator

@ShahinHaque97-CT , FYI

NXP added support for multiple memories on a single FlexSPI, see this merged PR #72528. Our plans changed from my previous comment. Trying to enable the MIMXRT685-EVK board, we found the limitations on that device do not allow simultaneous use of the two memories on that board. But we were able enable this on the RD-RW612-BGA board. Best regards

1 reply

ShahinHaque97-CT May 23, 2024
Author

@DerekSnell This is great news!, I will try this as soon as I have a board created with 2 flash ICs on the same FlexSPI as I have moved my second flash IC to a regular SPI, and let you know my findings!

matt-wood-ct · 2024-05-28T14:10:34Z

matt-wood-ct
May 28, 2024

@DerekSnell I gave this a test today, I can confirm it still does not work on the IMXRT104X series chips, test was as follows:
Using zephyr main (5a8652b):

Added second CS mapping:

<&iomuxc_gpio_sd_b0_00_flexspi_a_ss1_b>,

Added second flash IC onto our boards device tree:

    secondary_flash: is25wp128_2@1 {
        compatible = "nxp,imx-flexspi-nor";
        size = <(DT_SIZE_M(16) * 8)>;
        reg = <1>;
        spi-max-frequency = <133000000>;
        status = "okay";
        jedec-id = [ef 40 18]; /* may be unused with this driver */
        erase-block-size = <4096>;
        write-block-size = <1>;
    };

Then I mapped a little FS partition onto it in our application overlay:

fstab {
  lfs2: lfs2 {
	  compatible = "zephyr,fstab,littlefs";
	  mount-point = "/lfs2";
	  partition = <&update_lfs_part>;
	  automount;
	  read-size = <16>;
	  prog-size = <16>;
	  cache-size = <64>;
	  lookahead-size = <32>;
	  block-cycles = <512>;
  };
};
...
&secondary_flash {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		update_lfs_part: partition@0 {
			reg = <0x00000000 DT_SIZE_M(15)>;
		};
	};
};

This did boot once and showed in the device tree and appeared to work, then I rebooted the device and it refused to boot at all, indicating when it formatted the LFS partition it actually overwrote part of the bootloader which was inside the main QSPI flash IC which is shares the bus with.

Partially censored log below:

*** Booting MCUboot v2.1.0-rc1 ***
*** Using Zephyr OS build v3.6.0-3316-g64f41309d104 ***
I: Starting bootloader
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x20000
I: Jumping to the first image slot
*** Booting Zephyr OS build v3.6.0-4842-g5a8652b0c220 ***
*removed items*
[00:00:01.620,000] <err> littlefs: WEST_TOPDIR/modules/fs/littlefs/lfs.c:1351: Corrupted dir pair at {0x0, 0x1}
[00:00:01.620,000] <wrn> littlefs: can't mount (LFS -84); formatting
*removed items*
uart:~$ fs ls lfs2
uart:~$ fs mkdir lfs2/test
uart:~$ fs ls lfs2
test/
uart:~$ device list
devices:
*removed items*
- is25wp128_2@1 (READY)
- is25wp064@0 (READY)
*removed items*
uart:~$

After rebooting following that log there was no more uart output at all, assumption: MCUboot was damaged

1 reply

matt-wood-ct May 28, 2024

Note, in the log above I did have MCUBoot from an older zephyr version, I did retest with a matching zephyr build bootloader, the behaviour is no different.

DerekSnell · 2024-05-28T19:56:21Z

DerekSnell
May 28, 2024
Collaborator

Hi @matt-wood-ct ,
Thank you for testing this. Based on what you shared, it seems the first slave select flexspi_a_ss0_b is active during the file system access, which then corrupts your code. Can you confirm that on your board?

The board we tested with multiple memories uses a slightly different implementation of the FlexSPI. It would be helpful to confirm the FlexSPI register settings after the FlexSPI is configured for both memories. Can you use a debugger and capture these FlexSPI registers for us on your board?

Thank you

2 replies

matt-wood-ct Jun 3, 2024

Hi @matt-wood-ct , Thank you for testing this. Based on what you shared, it seems the first slave select flexspi_a_ss0_b is active during the file system access, which then corrupts your code. Can you confirm that on your board?

The board we tested with multiple memories uses a slightly different implementation of the FlexSPI. It would be helpful to confirm the FlexSPI register settings after the FlexSPI is configured for both memories. Can you use a debugger and capture these FlexSPI registers for us on your board?

Thank you

Hi @DerekSnell
I just got that board out again and attached to it (it refuses to get past MCUboot now), but I did manage to get the FlexSPI registers, see below

Peripheral, Register, Value, Fields
FLEXSPI, MCR0, 0xFFFF8010, SWRESET: 0b0; MDIS: 0b0; RXCLKSRC: val1; ARDFEN: val0; ATDFEN: val0; SERCLKDIV: val0; HSEN: val0; DOZEEN: val0; COMBINATIONEN: DISABLE; SCKFREERUNEN: DISABLE; IPGRANTWAIT: 0b11111111; AHBGRANTWAIT: 0b11111111
FLEXSPI, MCR1, 0xD3EEFFFF, AHBBUSWAIT: 0b1111111111111111; SEQWAIT: 0b1101001111101110
FLEXSPI, MCR2, 0x200001F7, CLRAHBBUFOPT: val0; SAMEDEVICEEN: individual_parallel; SCKBDIFFOPT: val1; RESUMEWAIT: 0b00100000
FLEXSPI, AHBCR, 0x00000078, APAREN: individual; CLRAHBRXBUF: 0b0; CLRAHBTXBUF: 0b0; CACHABLEEN: val1; BUFFERABLEEN: val1; PREFETCHEN: 0b1; READADDROPT: val1; READSZALIGN: val0
FLEXSPI, INTEN, 0x00000000, IPCMDDONEEN: 0b0; IPCMDGEEN: 0b0; AHBCMDGEEN: 0b0; IPCMDERREN: 0b0; AHBCMDERREN: 0b0; IPRXWAEN: 0b0; IPTXWEEN: 0b0; SCKSTOPBYRDEN: 0b0; SCKSTOPBYWREN: 0b0; AHBBUSTIMEOUTEN: 0b0; SEQTIMEOUTEN: 0b0
FLEXSPI, INTR, 0x00000041, IPCMDDONE: 0b1; IPCMDGE: 0b0; AHBCMDGE: 0b0; IPCMDERR: 0b0; AHBCMDERR: 0b0; IPRXWA: 0b0; IPTXWE: 0b1; SCKSTOPBYRD: 0b0; SCKSTOPBYWR: 0b0; AHBBUSTIMEOUT: 0b0; SEQTIMEOUT: 0b0
FLEXSPI, LUTKEY, 0x5AF05AF0, KEY: 0b01011010111100000101101011110000
FLEXSPI, LUTCR, 0x00000001, LOCK: 0b1; UNLOCK: 0b0
FLEXSPI, AHBRXBUF0CR0, 0x80000000, BUFSZ: 0b00000000; MSTRID: 0b0000; PRIORITY: 0b00; REGIONEN: 0b0; PREFETCHEN: 0b1
FLEXSPI, AHBRXBUF1CR0, 0x80000000, BUFSZ: 0b00000000; MSTRID: 0b0000; PRIORITY: 0b00; REGIONEN: 0b0; PREFETCHEN: 0b1
FLEXSPI, AHBRXBUF2CR0, 0x80000000, BUFSZ: 0b00000000; MSTRID: 0b0000; PRIORITY: 0b00; REGIONEN: 0b0; PREFETCHEN: 0b1
FLEXSPI, AHBRXBUF3CR0, 0x80030020, BUFSZ: 0b00100000; MSTRID: 0b0011; PRIORITY: 0b00; REGIONEN: 0b0; PREFETCHEN: 0b1
FLEXSPI, FLSHA1CR0, 0x00004000, FLSHSZ: 0b00000000100000000000000
FLEXSPI, FLSHA2CR0, 0x00000000, FLSHSZ: 0b00000000000000000000000
FLEXSPI, FLSHB1CR0, 0x00000000, FLSHSZ: 0b00000000000000000000000
FLEXSPI, FLSHB2CR0, 0x00000000, FLSHSZ: 0b00000000000000000000000
FLEXSPI, FLSHCR1A1, 0x00000063, TCSS: 0b00011; TCSH: 0b00011; WA: 0b0; CAS: 0b0000; CSINTERVALUNIT: val0; CSINTERVAL: 0b0000000000000000
FLEXSPI, FLSHCR1A2, 0x00000063, TCSS: 0b00011; TCSH: 0b00011; WA: 0b0; CAS: 0b0000; CSINTERVALUNIT: val0; CSINTERVAL: 0b0000000000000000
FLEXSPI, FLSHCR1B1, 0x00000063, TCSS: 0b00011; TCSH: 0b00011; WA: 0b0; CAS: 0b0000; CSINTERVALUNIT: val0; CSINTERVAL: 0b0000000000000000
FLEXSPI, FLSHCR1B2, 0x00000063, TCSS: 0b00011; TCSH: 0b00011; WA: 0b0; CAS: 0b0000; CSINTERVALUNIT: val0; CSINTERVAL: 0b0000000000000000
FLEXSPI, FLSHCR2A1, 0x00000000, ARDSEQID: 0b0000; ARDSEQNUM: 0b000; AWRSEQID: 0b0000; AWRSEQNUM: 0b000; AWRWAIT: 0b000000000000; AWRWAITUNIT: val0; CLRINSTRPTR: 0b0
FLEXSPI, FLSHCR2A2, 0x00000900, ARDSEQID: 0b0000; ARDSEQNUM: 0b000; AWRSEQID: 0b1001; AWRSEQNUM: 0b000; AWRWAIT: 0b000000000000; AWRWAITUNIT: val0; CLRINSTRPTR: 0b0
FLEXSPI, FLSHCR2B1, 0x00000900, ARDSEQID: 0b0000; ARDSEQNUM: 0b000; AWRSEQID: 0b1001; AWRSEQNUM: 0b000; AWRWAIT: 0b000000000000; AWRWAITUNIT: val0; CLRINSTRPTR: 0b0
FLEXSPI, FLSHCR2B2, 0x00000900, ARDSEQID: 0b0000; ARDSEQNUM: 0b000; AWRSEQID: 0b1001; AWRSEQNUM: 0b000; AWRWAIT: 0b000000000000; AWRWAITUNIT: val0; CLRINSTRPTR: 0b0
FLEXSPI, FLSHCR4, 0x00000001, WMOPT1: ENABLE; WMENA: val0; WMENB: val0
FLEXSPI, IPCR0, 0x00000000, SFAR: 0b00000000000000000000000000000000
FLEXSPI, IPCR1, 0x00060003, IDATSZ: 0b0000000000000011; ISEQID: 0b0110; ISEQNUM: 0b000; IPAREN: DISABLE
FLEXSPI, IPCMD, 0x00000000, TRG: 0b0
FLEXSPI, IPRXFCR, 0x00000000, CLRIPRXF: 0b0; RXDMAEN: val0; RXWMRK: 0b0000
FLEXSPI, IPTXFCR, 0x00000000, CLRIPTXF: 0b0; TXDMAEN: val0; TXWMRK: 0b0000
FLEXSPI, DLLCRA, 0x00000100, DLLEN: 0b0; DLLRESET: 0b0; SLVDLYTARGET: 0b0000; OVRDEN: 0b1; OVRDVAL: 0b000000
FLEXSPI, DLLCRB, 0x00000100, DLLEN: 0b0; DLLRESET: 0b0; SLVDLYTARGET: 0b0000; OVRDEN: 0b1; OVRDVAL: 0b000000
FLEXSPI, STS0, 0x00000003, SEQIDLE: 0b1; ARBIDLE: 0b1; ARBCMDSRC: val0
FLEXSPI, STS1, 0x00000000, AHBCMDERRID: 0b0000; AHBCMDERRCODE: val0; IPCMDERRID: 0b0000; IPCMDERRCODE: val0
FLEXSPI, STS2, 0x00000000, ASLVLOCK: 0b0; AREFLOCK: 0b0; ASLVSEL: 0b000000; AREFSEL: 0b000000; BSLVLOCK: 0b0; BREFLOCK: 0b0; BSLVSEL: 0b000000; BREFSEL: 0b000000
FLEXSPI, AHBSPNDSTS, 0x00000000, ACTIVE: 0b0; BUFID: 0b000; DATLFT: 0b0000000000000000
FLEXSPI, IPRXFSTS, 0x00010000, FILL: 0b00000000; RDCNTR: 0b0000000000000001
FLEXSPI, IPTXFSTS, 0x00000000, FILL: 0b00000000; WRCNTR: 0b0000000000000000
FLEXSPI, RFDR[0], 0x6B08EB44, RXDATA: 0b01101011000010001110101101000100
FLEXSPI, RFDR[1], 0xBB423B08, RXDATA: 0b10111011010000100011101100001000
FLEXSPI, RFDR[2], 0xFFFFFFFE, RXDATA: 0b11111111111111111111111111111110
FLEXSPI, RFDR[3], 0x0000FFFF, RXDATA: 0b00000000000000001111111111111111
FLEXSPI, RFDR[4], 0xEB40FFFF, RXDATA: 0b11101011010000001111111111111111
FLEXSPI, RFDR[5], 0x520F200C, RXDATA: 0b01010010000011110010000000001100
FLEXSPI, RFDR[6], 0x0000D810, RXDATA: 0b00000000000000001101100000010000
FLEXSPI, RFDR[7], 0x00A60236, RXDATA: 0b00000000101001100000001000110110
FLEXSPI, RFDR[8], 0xC914EA82, RXDATA: 0b11001001000101001110101010000010
FLEXSPI, RFDR[9], 0x337663E9, RXDATA: 0b00110011011101100110001111101001
FLEXSPI, RFDR[10], 0x757A757A, RXDATA: 0b01110101011110100111010101111010
FLEXSPI, RFDR[11], 0x5CD5A2F7, RXDATA: 0b01011100110101011010001011110111
FLEXSPI, RFDR[12], 0xFF4DF719, RXDATA: 0b11111111010011011111011100011001
FLEXSPI, RFDR[13], 0x80F830E9, RXDATA: 0b10000000111110000011000011101001
FLEXSPI, RFDR[14], 0x7A39915B, RXDATA: 0b01111010001110011001000101011011
FLEXSPI, RFDR[15], 0x9ACFBBB5, RXDATA: 0b10011010110011111011101110110101
FLEXSPI, RFDR[16], 0xA66A6B4B, RXDATA: 0b10100110011010100110101101001011
FLEXSPI, RFDR[17], 0x38DC9BB4, RXDATA: 0b00111000110111001001101110110100
FLEXSPI, RFDR[18], 0x3964D0E3, RXDATA: 0b00111001011001001101000011100011
FLEXSPI, RFDR[19], 0x788C6B3B, RXDATA: 0b01111000100011000110101100111011
FLEXSPI, RFDR[20], 0x631F6F3F, RXDATA: 0b01100011000111110110111100111111
FLEXSPI, RFDR[21], 0xB051686D, RXDATA: 0b10110000010100010110100001101101
FLEXSPI, RFDR[22], 0xAF16F939, RXDATA: 0b10101111000101101111100100111001
FLEXSPI, RFDR[23], 0xB497B6EC, RXDATA: 0b10110100100101111011011011101100
FLEXSPI, RFDR[24], 0xE1108B27, RXDATA: 0b11100001000100001000101100100111
FLEXSPI, RFDR[25], 0xA3841DAA, RXDATA: 0b10100011100001000001110110101010
FLEXSPI, RFDR[26], 0xECA0CB7C, RXDATA: 0b11101100101000001100101101111100
FLEXSPI, RFDR[27], 0xB6A36B23, RXDATA: 0b10110110101000110110101100100011
FLEXSPI, RFDR[28], 0xB00A607F, RXDATA: 0b10110000000010100110000001111111
FLEXSPI, RFDR[29], 0x00A60060, RXDATA: 0b00000000101001100000000001100000
FLEXSPI, RFDR[30], 0x001840EF, RXDATA: 0b00000000000110000100000011101111
FLEXSPI, RFDR[31], 0x00000000, RXDATA: 0b00000000000000000000000000000000
FLEXSPI, TFDR[0], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[1], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[2], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[3], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[4], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[5], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[6], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[7], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[8], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[9], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[10], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[11], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[12], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[13], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[14], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[15], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[16], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[17], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[18], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[19], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[20], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[21], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[22], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[23], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[24], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[25], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[26], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[27], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[28], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[29], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[30], <Write-Only>, TXDATA: -
FLEXSPI, TFDR[31], <Write-Only>, TXDATA: -
FLEXSPI, LUT[0], 0x0A1804EB, OPERAND0: 0b11101011; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00011000; NUM_PADS1: 0b10; OPCODE1: 0b000010
FLEXSPI, LUT[1], 0x32041E00, OPERAND0: 0b00000000; NUM_PADS0: 0b10; OPCODE0: 0b000111; OPERAND1: 0b00000100; NUM_PADS1: 0b10; OPCODE1: 0b001100
FLEXSPI, LUT[2], 0x00002604, OPERAND0: 0b00000100; NUM_PADS0: 0b10; OPCODE0: 0b001001; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[3], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[4], 0x08180432, OPERAND0: 0b00110010; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00011000; NUM_PADS1: 0b00; OPCODE1: 0b000010
FLEXSPI, LUT[5], 0x00002204, OPERAND0: 0b00000100; NUM_PADS0: 0b10; OPCODE0: 0b001000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[6], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[7], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[8], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[9], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[10], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[11], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[12], 0x00000406, OPERAND0: 0b00000110; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[13], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[14], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[15], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[16], 0x08180420, OPERAND0: 0b00100000; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00011000; NUM_PADS1: 0b00; OPCODE1: 0b000010
FLEXSPI, LUT[17], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[18], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[19], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[20], 0x081804D8, OPERAND0: 0b11011000; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00011000; NUM_PADS1: 0b00; OPCODE1: 0b000010
FLEXSPI, LUT[21], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[22], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[23], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[24], 0x2401049F, OPERAND0: 0b10011111; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00000001; NUM_PADS1: 0b00; OPCODE1: 0b001001
FLEXSPI, LUT[25], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[26], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[27], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[28], 0x24010405, OPERAND0: 0b00000101; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00000001; NUM_PADS1: 0b00; OPCODE1: 0b001001
FLEXSPI, LUT[29], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[30], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[31], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[32], 0x000004C7, OPERAND0: 0b11000111; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[33], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[34], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[35], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[36], 0x0818045A, OPERAND0: 0b01011010; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00011000; NUM_PADS1: 0b00; OPCODE1: 0b000010
FLEXSPI, LUT[37], 0x24043008, OPERAND0: 0b00001000; NUM_PADS0: 0b00; OPCODE0: 0b001100; OPERAND1: 0b00000100; NUM_PADS1: 0b00; OPCODE1: 0b001001
FLEXSPI, LUT[38], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[39], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[40], 0x24010405, OPERAND0: 0b00000101; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00000001; NUM_PADS1: 0b00; OPCODE1: 0b001001
FLEXSPI, LUT[41], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[42], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[43], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[44], 0x20010401, OPERAND0: 0b00000001; NUM_PADS0: 0b00; OPCODE0: 0b000001; OPERAND1: 0b00000001; NUM_PADS1: 0b00; OPCODE1: 0b001000
FLEXSPI, LUT[45], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[46], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[47], 0x00000000, OPERAND0: 0b00000000; NUM_PADS0: 0b00; OPCODE0: 0b000000; OPERAND1: 0b00000000; NUM_PADS1: 0b00; OPCODE1: 0b000000
FLEXSPI, LUT[48], 0xF91CBC35, OPERAND0: 0b00110101; NUM_PADS0: 0b00; OPCODE0: 0b101111; OPERAND1: 0b00011100; NUM_PADS1: 0b01; OPCODE1: 0b111110
FLEXSPI, LUT[49], 0x02FCE1FB, OPERAND0: 0b11111011; NUM_PADS0: 0b01; OPCODE0: 0b111000; OPERAND1: 0b11111100; NUM_PADS1: 0b10; OPCODE1: 0b000000
FLEXSPI, LUT[50], 0xE02D67B9, OPERAND0: 0b10111001; NUM_PADS0: 0b11; OPCODE0: 0b011001; OPERAND1: 0b00101101; NUM_PADS1: 0b00; OPCODE1: 0b111000
FLEXSPI, LUT[51], 0x8EE64CE3, OPERAND0: 0b11100011; NUM_PADS0: 0b00; OPCODE0: 0b010011; OPERAND1: 0b11100110; NUM_PADS1: 0b10; OPCODE1: 0b100011
FLEXSPI, LUT[52], 0x0B4CCF92, OPERAND0: 0b10010010; NUM_PADS0: 0b11; OPCODE0: 0b110011; OPERAND1: 0b01001100; NUM_PADS1: 0b11; OPCODE1: 0b000010
FLEXSPI, LUT[53], 0x269FB131, OPERAND0: 0b00110001; NUM_PADS0: 0b01; OPCODE0: 0b101100; OPERAND1: 0b10011111; NUM_PADS1: 0b10; OPCODE1: 0b001001
FLEXSPI, LUT[54], 0xC1CCA28E, OPERAND0: 0b10001110; NUM_PADS0: 0b10; OPCODE0: 0b101000; OPERAND1: 0b11001100; NUM_PADS1: 0b01; OPCODE1: 0b110000
FLEXSPI, LUT[55], 0x9406CFA9, OPERAND0: 0b10101001; NUM_PADS0: 0b11; OPCODE0: 0b110011; OPERAND1: 0b00000110; NUM_PADS1: 0b00; OPCODE1: 0b100101
FLEXSPI, LUT[56], 0x808CD0FA, OPERAND0: 0b11111010; NUM_PADS0: 0b00; OPCODE0: 0b110100; OPERAND1: 0b10001100; NUM_PADS1: 0b00; OPCODE1: 0b100000
FLEXSPI, LUT[57], 0xEBC78218, OPERAND0: 0b00011000; NUM_PADS0: 0b10; OPCODE0: 0b100000; OPERAND1: 0b11000111; NUM_PADS1: 0b11; OPCODE1: 0b111010
FLEXSPI, LUT[58], 0x84C2CE72, OPERAND0: 0b01110010; NUM_PADS0: 0b10; OPCODE0: 0b110011; OPERAND1: 0b11000010; NUM_PADS1: 0b00; OPCODE1: 0b100001
FLEXSPI, LUT[59], 0xD4F1D39F, OPERAND0: 0b10011111; NUM_PADS0: 0b11; OPCODE0: 0b110100; OPERAND1: 0b11110001; NUM_PADS1: 0b00; OPCODE1: 0b110101
FLEXSPI, LUT[60], 0xABE74828, OPERAND0: 0b00101000; NUM_PADS0: 0b00; OPCODE0: 0b010010; OPERAND1: 0b11100111; NUM_PADS1: 0b11; OPCODE1: 0b101010
FLEXSPI, LUT[61], 0x88AC2020, OPERAND0: 0b00100000; NUM_PADS0: 0b00; OPCODE0: 0b001000; OPERAND1: 0b10101100; NUM_PADS1: 0b00; OPCODE1: 0b100010
FLEXSPI, LUT[62], 0xDE369E6C, OPERAND0: 0b01101100; NUM_PADS0: 0b10; OPCODE0: 0b100111; OPERAND1: 0b00110110; NUM_PADS1: 0b10; OPCODE1: 0b110111
FLEXSPI, LUT[63], 0x67848049, OPERAND0: 0b01001001; NUM_PADS0: 0b00; OPCODE0: 0b100000; OPERAND1: 0b10000100; NUM_PADS1: 0b11; OPCODE1: 0b011001

danieldegrasse Jun 3, 2024
Collaborator

Thanks for providing this, @matt-wood-ct. Looking at the FLSHxCR0 registers, it seems that FLSHSZ is only set for the flash on port A1. Could you check within a debugger to see if FLEXSPI_SetFlashConfig is called for both ports kFLEXSPI_PortA1 and kFLEXSPI_PortA2? Another thing to check would be if flash_flexspi_nor_init is being called twice- once for each flash device.

multiple imx-flexspi-nor flash ICs #57483

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ShahinHaque97-CT May 2, 2023

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DerekSnell May 2, 2023 Collaborator

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yunheQin Jan 26, 2024

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DerekSnell Jan 26, 2024 Collaborator

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ShahinHaque97-CT Mar 17, 2024 Author

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DerekSnell Mar 18, 2024 Collaborator

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ShahinHaque97-CT May 3, 2023 Author

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DerekSnell May 23, 2024 Collaborator

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ShahinHaque97-CT May 23, 2024 Author

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matt-wood-ct May 28, 2024

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matt-wood-ct May 28, 2024

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DerekSnell May 28, 2024 Collaborator

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matt-wood-ct Jun 3, 2024

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danieldegrasse Jun 3, 2024 Collaborator

ShahinHaque97-CT
May 2, 2023

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DerekSnell
May 2, 2023
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DerekSnell Jan 26, 2024
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ShahinHaque97-CT Mar 17, 2024
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DerekSnell Mar 18, 2024
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ShahinHaque97-CT
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DerekSnell
May 23, 2024
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ShahinHaque97-CT May 23, 2024
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matt-wood-ct
May 28, 2024

DerekSnell
May 28, 2024
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danieldegrasse Jun 3, 2024
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