Upll clock #49080
Upll clock
#49080
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i used can driver which used plla clock and i was able to send message with low bitrate, when i switched to can driver that uses upll clock i am getting error "can_mcan can not leave init mode". I am using same70j19 custom board. Can you help me to fix this problem? |
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Answered by
henrikbrixandersen
Aug 15, 2022
Replies: 2 comments
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You already asked this in #45012 (comment) and received a reply in #45012 (comment). |
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Answer selected by
henrikbrixandersen
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Sorry, but this is not an answer, i have a Crystal oscillator, but unfortunately it is not working for me. I am wondering if i was able to use Driver with plla Clock, why i can not use the one with upll Clock.
Von: Henrik Brix ***@***.***>
Gesendet: Montag, 15. August 2022 21:22
An: ***@***.***>
Cc: ***@***.***>; ***@***.***>
Betreff: Re: [zephyrproject-rtos/zephyr] Upll clock (Discussion #49080)
You already asked this in #45012 (comment)<#45012 (comment)> and received a reply in #45012 (comment)<#45012 (comment)>.
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Reply to this email directly, view it on GitHub<#49080 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/ARBSPZITA24G55KZJD6KBJDVZKKGDANCNFSM56TG4NOA>.
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You already asked this in #45012 (comment) and received a reply in #45012 (comment).