Implementing imx8MN board. #49061
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JaagupAverin
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For the sram0 address, you can use the same value with IMX8MM "0x93c00000", it is ram address used by Zephyr and specified by dts or CONFIG_SRAM_BASE_ADDRESS and CONFIG_SRAM_SIZE. If you boot Zephyr from uboot, you should use the same memory address to load and run Zephyr. If you use Jailhouse, the address should be same with the memory address in inmate cell configuration. For the number of CPU Cores, current code in Zephyr community doesn't enable SMP, so only Core0 is used. Finally, for IMX8MN platform support in Zephyr, NXP will upstream it to community soon, and it will enable SMP. |
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Hello.
I am trying to build a Zephyr application for the imx8MN devkit. A board for imx8MM devkit has already been implemented. However I am having trouble getting the Nano version of the board to work.
I have duplicated the existing board folder, but some things are unclear to me, such as what the sram0 value should be pointing to, and where it came from from in the existing imx8MM code.
Furthermore, a dts has been implemented for the imx8MM board as seen here, however this implementation also confuses me, as it specifies 2 cores, whereas the actual devkit should have 4 cores.
Finally, what else should be changed (in terms of registers and sizes) when converting the existing Mini board to a Nano board? I have many gaps in understanding when it comes to devicetree and board implementation so any answers and general direction is very welcome!
Thank you.
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