Device tree error while porting zephyr for a custom board

[1priya-1]

devicetree error: unexpected 'interrupt-cells:' length in binding for <Node /soc/interrupt-controller@c000000 in '/home/zephyrproject/zephyr/misc/empty_file.c'> - 2 instead of 1

I am trying to build zephyr for a custom soc+board,I have followed the steps as in the main website.Now i am stuck at this device tree error.
I am targeting a riscv based platform.The interrupt controller is compatible with riscv,plic and it has interrupt cells <1>.

[gmarull]

Please provide a way to reproduce the problem, otherwise it's hard to investigate issues.

[carlescufi]

@mbolivar-nordic any input here?

[mbolivar-nordic]

There isn't enough information here for me to provide input.

[1priya-1]

riscv64_rocketchip.zip
I am trying to port Zephyr into riscv based SoC(Rocketchip).I have a rocketchip folder in boards/riscv/ section.

1. added the dts file for nexys_video fpga into that,and kconfig.board,kconfig.defconfig file
   ->The dts file used is system_nexys_video.dts file from the rocketchip (Eugene tarrasov) repositry.
   2)on soc/riscv section I added kconfig.defconfig,soc.h,linker.ld,cmakelists.txt files which I am not sure about.I reffered to the litex_vexriscv section.

cmake -B build -GNinja -DBOARD=rocketchip samples/hello_world.

This is the command i am using,which results in the above mentioned device tree error.

[1priya-1]

To Reproduce
Steps to reproduce the behavior:

cd zephyrproject/zephyr
rm -rf build
cmake -B build -GNinja -DBOARD=rocketchip samples/hello_world.

->soc
soc.zip

->boards/riscv/rocketchip
rocketchip.zip
->dtsi file used
riscv64_rocketchip.zip
See error

[mbolivar-nordic]

Hi, thanks for adding some more information, but this is not really giving steps to reproduce and it is sent in a way that is wasting our time.

Making us download and unzip several different zip files, some of which contain quite a lot of unrelated code, is forcing us to do a lot of work to try to figure out what's wrong with your setup. Please don't waste our time like this.

Here are some specific problems:

->soc
soc.zip

There are more than 3,000 files in here. Most of them are not related to your problem as they are just copies of existing code in the soc tree. It's not really clear what you expect us to do with this.

->boards/riscv/rocketchip
rocketchip.zip

This contains various vim backup files that aren't relevant to your question.

->dtsi file used
riscv64_rocketchip.zip

In here, I see:

 123   │         L8: interrupt-controller@c000000 {
 124   │             #interrupt-cells = <1>;
 125   │             compatible = "riscv,plic0";

This looks suspicious for multiple reasons:

• This is not a compatible property with any binding in upstream zephyr. There is

  zephyr/dts/bindings/interrupt-controller/riscv,plic0.yaml

  Line 4 in 82ac3fa

  # Common fields for the RISC-V platform-local interrupt controller

  , but this is meant as an include file because it does not actually define a binding for the compatible riscv,plic0.
• There doesn't appear to be a binding for this compatible in the zip files you sent, although again since they contain many unrelated things it's hard to really say for sure.
• The upstream include file says that #interrupt-cells for this type of interrupt controller should be 2, not 1 as your DTSI file has written in it. But since there is no binding for this compatible in anything you've shared or that I can see, I think that you probably have written a binding for this somewhere and not shared it.

I would like to help you but you need to show me something smaller that I can use to reproduce that doesn't require me to read your mind or figure out what bindings you might not have shared.

Ideally push an actual git branch to a public zephyr fork and put a link to it here, so we can see exactly what you did without having to reconstruct things for you on our own computers from various zip files.