can_sam.c

[CEmir10]

I would like to ask you if someone can help me to achive CAN clock at frequencies of 20, 40 or 80 MHz. To achieve these frequencies, PMC PCK5 must select the UPLLCK (480 MHz) as source clock and divide by 24,12, or 6. PCK5 allows the system bus
and processor clock to be modified without affecting the bit rate communication. I see that UPLLCK is not selected in can_sam.c

[nandojve]

CC: @alexanderwachter

[alexanderwachter]

You can implement such things in the SAM CAN driver frontend. I would recommend putting the clk source/dividers in the device tree. You need to change the function that returns the clock speed too, so that the timing calculation algorithm can set the correct bitrate and sampling point for you.