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boards: adi: Add both HyperRAM banks to APARD32690
Add the correct HypeBus setup for both banks of HypeRAM found on the APARD32690 board. Signed-off-by: Pete Johanson <pete.johanson@analog.com>
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boards/adi/apard32690/apard32690_max32690_m4.dts

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@@ -9,6 +9,7 @@
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#include <adi/max32/max32690.dtsi>
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#include <adi/max32/max32690-pinctrl.dtsi>
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#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
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#include <zephyr/dt-bindings/memory-controller/adi-max32-hpb.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
@@ -82,6 +83,22 @@
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<20 0 &gpio2 17 0>, /* D14 */
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<21 0 &gpio2 18 0>; /* D15 */
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};
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sdram1: sdram1@60000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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status = "disabled";
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device_type = "memory";
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reg = <0x60000000 DT_SIZE_M(64)>;
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zephyr,memory-region = "SDRAM1";
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};
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sdram2: sdram2@70000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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status = "disabled";
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device_type = "memory";
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reg = <0x70000000 DT_SIZE_M(64)>;
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zephyr,memory-region = "SDRAM2";
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};
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};
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&clk_ipo {
@@ -227,3 +244,52 @@ pmod_spi: &spi4 {
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pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>;
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pinctrl-names = "default";
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};
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&hpb {
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pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_cs1n_p1_17 &hyp_rwds_p1_14
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&hyp_d0_p1_12 &hyp_d1_p1_15
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&hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13
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&hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>;
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pinctrl-names = "default";
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enable-emcc;
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mem@0 {
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reg = <0>;
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base-address = <0x60000000>;
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device-type = <ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM>;
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latency-cycles = <ADI_MAX32_HPB_LAT_6>;
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read-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>;
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write-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>;
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read-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_16>;
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write-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_14>;
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read-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_5>;
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write-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_12>;
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/* CR0 settings. Key setting is enabling 6-clock latency, since
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* HPB doesn't support 7-clock latency which is default
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*/
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config-regs = <0x1000>;
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config-reg-vals = <0x801F>;
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};
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mem@1 {
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reg = <1>;
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base-address = <0x70000000>;
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device-type = <ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM>;
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latency-cycles = <ADI_MAX32_HPB_LAT_6>;
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read-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>;
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write-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>;
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read-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_16>;
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write-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_14>;
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read-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_5>;
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write-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_12>;
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/* CR0 settings. Key setting is enabling 6-clock latency, since
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* HPB doesn't support 7-clock latency which is default
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*/
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config-regs = <0x1000>;
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config-reg-vals = <0x801F>;
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};
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};

boards/adi/apard32690/apard32690_max32690_m4.yaml

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@@ -17,5 +17,6 @@ supported:
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- trng
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- counter
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- w1
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- memc
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ram: 1024
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flash: 3072

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