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9 | 9 | #include <adi/max32/max32690.dtsi>
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10 | 10 | #include <adi/max32/max32690-pinctrl.dtsi>
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11 | 11 | #include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
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| 12 | +#include <zephyr/dt-bindings/memory-controller/adi-max32-hpb.h> |
12 | 13 | #include <zephyr/dt-bindings/input/input-event-codes.h>
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13 | 14 |
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14 | 15 | / {
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82 | 83 | <20 0 &gpio2 17 0>, /* D14 */
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83 | 84 | <21 0 &gpio2 18 0>; /* D15 */
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84 | 85 | };
|
| 86 | + |
| 87 | + sdram1: sdram1@60000000 { |
| 88 | + compatible = "zephyr,memory-region", "mmio-sram"; |
| 89 | + status = "disabled"; |
| 90 | + device_type = "memory"; |
| 91 | + reg = <0x60000000 DT_SIZE_M(64)>; |
| 92 | + zephyr,memory-region = "SDRAM1"; |
| 93 | + }; |
| 94 | + |
| 95 | + sdram2: sdram2@70000000 { |
| 96 | + compatible = "zephyr,memory-region", "mmio-sram"; |
| 97 | + status = "disabled"; |
| 98 | + device_type = "memory"; |
| 99 | + reg = <0x70000000 DT_SIZE_M(64)>; |
| 100 | + zephyr,memory-region = "SDRAM2"; |
| 101 | + }; |
85 | 102 | };
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86 | 103 |
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87 | 104 | &clk_ipo {
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@@ -227,3 +244,52 @@ pmod_spi: &spi4 {
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227 | 244 | pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>;
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228 | 245 | pinctrl-names = "default";
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229 | 246 | };
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| 247 | + |
| 248 | +&hpb { |
| 249 | + pinctrl-0 = <&hyp_cs0n_p1_11 &hyp_cs1n_p1_17 &hyp_rwds_p1_14 |
| 250 | + &hyp_d0_p1_12 &hyp_d1_p1_15 |
| 251 | + &hyp_d2_p1_19 &hyp_d3_p1_20 &hyp_d4_p1_13 |
| 252 | + &hyp_d5_p1_16 &hyp_d6_p1_18 &hyp_d7_p1_21>; |
| 253 | + pinctrl-names = "default"; |
| 254 | + enable-emcc; |
| 255 | + |
| 256 | + mem@0 { |
| 257 | + reg = <0>; |
| 258 | + base-address = <0x60000000>; |
| 259 | + device-type = <ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM>; |
| 260 | + |
| 261 | + latency-cycles = <ADI_MAX32_HPB_LAT_6>; |
| 262 | + read-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>; |
| 263 | + write-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>; |
| 264 | + read-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_16>; |
| 265 | + write-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_14>; |
| 266 | + read-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_5>; |
| 267 | + write-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_12>; |
| 268 | + |
| 269 | + /* CR0 settings. Key setting is enabling 6-clock latency, since |
| 270 | + * HPB doesn't support 7-clock latency which is default |
| 271 | + */ |
| 272 | + config-regs = <0x1000>; |
| 273 | + config-reg-vals = <0x801F>; |
| 274 | + }; |
| 275 | + |
| 276 | + mem@1 { |
| 277 | + reg = <1>; |
| 278 | + base-address = <0x70000000>; |
| 279 | + device-type = <ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM>; |
| 280 | + |
| 281 | + latency-cycles = <ADI_MAX32_HPB_LAT_6>; |
| 282 | + read-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>; |
| 283 | + write-cs-high = <ADI_MAX32_HPB_CS_HIGH_10_5>; |
| 284 | + read-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_16>; |
| 285 | + write-cs-setup = <ADI_MAX32_HPB_CS_SETUP_HOLD_14>; |
| 286 | + read-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_5>; |
| 287 | + write-cs-hold = <ADI_MAX32_HPB_CS_SETUP_HOLD_12>; |
| 288 | + |
| 289 | + /* CR0 settings. Key setting is enabling 6-clock latency, since |
| 290 | + * HPB doesn't support 7-clock latency which is default |
| 291 | + */ |
| 292 | + config-regs = <0x1000>; |
| 293 | + config-reg-vals = <0x801F>; |
| 294 | + }; |
| 295 | +}; |
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