soc: Make BL60x independant from SDK

Reorganize and update soc folder files for SDK-independance

Signed-off-by: Camille BAUD <mail@massdriver.space>

Author: VynDragon

soc/bflb/Kconfig

@@ -2,9 +2,6 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_FAMILY_BFLB
-	select HAS_BFLB_HAL
-
 if SOC_FAMILY_BFLB
 
 rsource "*/Kconfig"

soc/bflb/bl60x/CMakeLists.txt

@@ -1,13 +1,13 @@
 # Copyright (c) 2021-2025 ATL Electronics
+# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
 #
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
 zephyr_sources(soc.c)
 
-zephyr_linker_sources_ifdef(CONFIG_SOC_SERIES_BL60X RODATA rodata.ld)
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
 
-set(SOC_LINKER_SCRIPT
-  ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld
-  CACHE INTERNAL ""
-  )
+zephyr_code_relocate_ifdef(CONFIG_UART_BFLB LIBRARY drivers__serial LOCATION ITCM NOKEEP)
+zephyr_code_relocate_ifdef(CONFIG_RISCV_MACHINE_TIMER LIBRARY drivers__timer LOCATION ITCM NOKEEP)
+zephyr_code_relocate_ifdef(CONFIG_PINCTRL_BFLB LIBRARY drivers__pinctrl LOCATION ITCM NOKEEP)

soc/bflb/bl60x/Kconfig

@@ -1,20 +1,30 @@
 # Copyright (c) 2021-2025 ATL Electronics
+# Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
 #
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_BL60X
 	select ATOMIC_OPERATIONS_C
 	select CLOCK_CONTROL
+	select CODE_DATA_RELOCATION
 	select CPU_HAS_FPU
+	select FLOAT_HARD
+	select FPU
+	select GEN_IRQ_VECTOR_TABLE
 	select INCLUDE_RESET_VECTOR
 	select RISCV
+	select RISCV_HAS_CLIC
 	select RISCV_MACHINE_TIMER
+	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
+	select RISCV_PRIVILEGED
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_F
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_VECTORED_MODE
 	select SOC_EARLY_INIT_HOOK
 	select SYSCON
 	select XIP

soc/bflb/bl60x/Kconfig.defconfig

@@ -4,7 +4,16 @@
 
 if SOC_SERIES_BL60X
 
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
 config NUM_IRQS
 	default 80
 
+config ARCH_SW_ISR_TABLE_ALIGN
+	default 64
+
+config RISCV_MCAUSE_EXCEPTION_MASK
+	default 0x3FF
+
 endif # SOC_SERIES_BL60X

soc/bflb/bl60x/rodata.ld

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021-2025 ATL Electronics
+ * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,37 +14,31 @@
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
 
-#include <bflb_hbn.h>
-#include <bflb_glb.h>
 #include <clic.h>
+#include <bflb_soc.h>
+#include <glb_reg.h>
+#include <hbn_reg.h>
+#include <pds_reg.h>
 
-#define ROOT_FCLK_DIV       (0)
-#define ROOT_BCLK_DIV       (1)
-#define ROOT_UART_CLOCK_DIV (0)
-
+/* Set Embedded Flash Pullup */
 static void system_bor_init(void)
 {
-	HBN_BOR_CFG_Type borCfg = { 1 /* pu_bor */,  0 /* irq_bor_en */,
-				    1 /* bor_vth */, 1 /* bor_sel */ };
-	HBN_Set_BOR_Cfg(&borCfg);
-}
+	uint32_t tmp = 0;
 
-static uint32_t mtimer_get_clk_src_div(void)
-{
-	return ((SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1))
-		/ 1000 / 1000 - 1);
-}
+	tmp = sys_read32(HBN_BASE + HBN_BOR_CFG_OFFSET);
+	/* borThreshold = 1 */
+	tmp = (tmp & HBN_BOR_VTH_UMSK) | ((uint32_t)(1) << HBN_BOR_VTH_POS);
+	/* enablePorInBor true*/
+	tmp = (tmp & HBN_BOR_SEL_UMSK) | ((uint32_t)(1) << HBN_BOR_SEL_POS);
+	/* enableBor true*/
+	tmp = (tmp & HBN_PU_BOR_UMSK) | ((uint32_t)(1) << HBN_PU_BOR_POS);
+	sys_write32(tmp, HBN_BASE + HBN_BOR_CFG_OFFSET);
 
-static void system_clock_init(void)
-{
-	GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL160M);
-	GLB_Set_System_CLK_Div(ROOT_FCLK_DIV, ROOT_BCLK_DIV);
-	GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
-}
 
-static void peripheral_clock_init(void)
-{
-	GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, ROOT_UART_CLOCK_DIV);
+	/* enableBorInt false */
+	tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET);
+	tmp = tmp & HBN_IRQ_BOR_EN_UMSK;
+	sys_write32(tmp, HBN_BASE + HBN_IRQ_MODE_OFFSET);
 }
 
 void soc_early_init_hook(void)
@@ -55,37 +50,37 @@ void soc_early_init_hook(void)
 
 	key = irq_lock();
 
-	__disable_irq();
 
 	/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
-	tmp = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
-	tmp = BL_CLR_REG_BIT(tmp, HBN_REG_EN_HW_PU_PD);
-	BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp);
+	tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET);
+	/* "BL_CLR_REG_BIT" */
+	tmp = tmp & HBN_REG_EN_HW_PU_PD_UMSK;
+	sys_write32(tmp, HBN_BASE + HBN_IRQ_MODE_OFFSET);
 
-	/* GLB_Set_EM_Sel(GLB_EM_0KB); */
-	tmp = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
-	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_EM_SEL, GLB_EM_0KB);
-	BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmp);
+	/* 'seam' 0kb, undocumented */
+	tmp = sys_read32(GLB_BASE + GLB_SEAM_MISC_OFFSET);
+	tmp = (tmp & GLB_EM_SEL_UMSK) | ((uint32_t)(0) << GLB_EM_SEL_POS);
+	sys_write32(tmp, GLB_BASE + GLB_SEAM_MISC_OFFSET);
 
 	/* Fix 26M xtal clkpll_sdmin */
-	tmp = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+	tmp = sys_read32(PDS_BASE + PDS_CLKPLL_SDM_OFFSET);
 
-	if (BL_GET_REG_BITS_VAL(tmp, PDS_CLKPLL_SDMIN) == 0x49D39D) {
-		tmp = BL_SET_REG_BITS_VAL(tmp, PDS_CLKPLL_SDMIN, 0x49D89E);
-		BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmp);
+	if ((tmp & PDS_CLKPLL_SDMIN_MSK) == 0x49D39D) {
+		tmp = (tmp & PDS_CLKPLL_SDMIN_UMSK) | (uint32_t)(0x49D89E);
+		sys_write32(tmp, PDS_BASE + PDS_CLKPLL_SDM_OFFSET);
 	}
 
-	/* Restore default setting*/
-
-	/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
-	tmp = BL_RD_REG(GLB_BASE, GLB_PARM);
-	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
-	BL_WR_REG(GLB_BASE, GLB_PARM, tmp);
-
+	tmp = sys_read32(GLB_BASE + GLB_PARM_OFFSET);
+	/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
+	 * no swap = 0
+	 * see bl602_glb.h for other possible values
+	 */
+	tmp = (tmp & GLB_UART_SWAP_SET_UMSK) | ((uint32_t)(0) <<
+GLB_UART_SWAP_SET_POS);
 	/* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */
-	tmp = BL_RD_REG(GLB_BASE, GLB_PARM);
-	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_JTAG_SWAP_SET, JTAG_SIG_SWAP_NONE);
-	BL_WR_REG(GLB_BASE, GLB_PARM, tmp);
+	tmp = (tmp & GLB_JTAG_SWAP_SET_UMSK) | ((uint32_t)(0) <<
+GLB_JTAG_SWAP_SET_POS);
+	sys_write32(tmp, GLB_BASE + GLB_PARM_OFFSET);
 
 	/* CLear all interrupt */
 	p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
@@ -102,21 +97,6 @@ void soc_early_init_hook(void)
 
 	/* init bor for all platform */
 	system_bor_init();
-	/* global IRQ enable */
-	__enable_irq();
-
-	system_clock_init();
-	peripheral_clock_init();
 
 	irq_unlock(key);
 }
-
-/* identify flash config automatically */
-extern BL_Err_Type flash_init(void);
-
-void System_Post_Init(void)
-{
-	PDS_Trim_RC32M();
-	HBN_Trim_RC32K();
-	flash_init();
-}

soc/bflb/bl60x/soc.c

@@ -15,35 +15,12 @@
 #define _SOC__H_
 
 #include <zephyr/sys/util.h>
-#include <../common/soc_common.h>
 
 #ifndef _ASMLANGUAGE
 
 /* Add include for DTS generated information */
 #include <zephyr/devicetree.h>
 
-#if defined(CONFIG_SOC_SERIES_BL60X)
-#include <bl602.h>
-#else
-#error Library does not support the specified device.
-#endif
-
-/* clang-format off */
-
-/* RISC-V Machine Timer configuration */
-#define RISCV_MTIME_BASE                  0x0200BFF8
-#define RISCV_MTIMECMP_BASE               0x02004000
-
-/* lib-c hooks required RAM defined variables */
-#define RISCV_RAM_BASE                    DT_SRAM_BASE_ADDRESS
-#define RISCV_RAM_SIZE                    KB(DT_SRAM_SIZE)
-
-#define SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ (160000000)
-#define SOC_BOUFFALOLAB_BL_HCLK_FREQ_HZ	\
-		DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
-
-/* clang-format on */
-
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _SOC__H_ */

soc/bflb/bl60x/soc.h

@@ -4,8 +4,9 @@
 
 zephyr_include_directories(.)
 
+if(CONFIG_SOC_SERIES_BL60X)
+zephyr_include_directories(e24)
 zephyr_sources(
-  soc_irq.S
-  soc_common_irq.c
-  vector.S
-  )
+e24/soc_irq_privileged.c
+e24/intc_clic.S)
+endif()

soc/bflb/common/CMakeLists.txt

@@ -23,4 +23,12 @@
 #define CLIC_INTCFG 0x800
 #define CLIC_CFG    0xc00
 
+/* CLIC relative CSR number */
+#define CSR_MTVT       (0x307)
+#define CSR_MNXTI      (0x345)
+#define CSR_MINTTHRESH (0x347)
+#define CSR_MISELECT   (0x350)
+#define CSR_MIREG      (0x351)
+#define CSR_MIREG2     (0x352)
+
 #endif /* _SIFIVE_CLIC_H */

soc/bflb/common/clic.h renamed to soc/bflb/common/e24/clic.h

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2024 Baumer Electric AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Assembler-hooks specific to RISC-V Core Local Interrupt Controller
+ */
+
+#include <zephyr/arch/cpu.h>
+#include "clic.h"
+
+
+/* register-wide load/store based on lw/sw (XLEN = 32) */
+
+.macro lr, rd, mem
+lw \rd, \mem
+.endm
+
+.macro sr, rs, mem
+sw \rs, \mem
+.endm
+
+
+GTEXT(__soc_handle_irq)
+/*
+ * In an CLIC, pending interrupts don't have to be cleared by hand.
+ * In vectored mode, interrupts are cleared automatically.
+ * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
+ * __soc_handle_all_irqs).
+ * Thus this function can directly return.
+ */
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	ret
+
+GTEXT(__soc_handle_all_irqs)
+
+#ifdef CONFIG_TRACING
+/* imports */
+GTEXT(sys_trace_isr_enter)
+GTEXT(sys_trace_isr_exit)
+#endif
+
+/*
+ * This function services and clears all pending interrupts for an CLIC in non-vectored mode.
+ */
+SECTION_FUNC(exception.other, __soc_handle_all_irqs)
+	addi sp, sp, -16
+	sr ra, 0(sp)
+
+	/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
+	 * original interrupt if no others appear. */
+	csrrci a0, CSR_MNXTI, MSTATUS_IEN
+	beqz a0, irq_done /* Check if original interrupt vanished. */
+
+irq_loop:
+
+#ifdef CONFIG_TRACING_ISR
+	call sys_trace_isr_enter
+#endif
+
+	/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
+	 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
+	csrr t0, CSR_MTVT
+	sub a0, a0, t0
+	la t0, _sw_isr_table
+	slli a0, a0, (1)
+	add t0, t0, a0
+
+	/* Load argument in a0 register */
+	lr a0, 0(t0)
+
+	/* Load ISR function address in register t1 */
+	lr t1, RV_REGSIZE(t0)
+
+	/* Call ISR function */
+	jalr ra, t1, 0
+
+#ifdef CONFIG_TRACING_ISR
+	call sys_trace_isr_exit
+#endif
+
+	/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
+	csrrci a0, CSR_MNXTI, MSTATUS_IEN
+	bnez a0, irq_loop
+
+irq_done:
+	lr ra, 0(sp)
+	addi sp, sp, 16
+	ret