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Add support for SiLabs EFR32ZG28 SoC
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# Copyright (c) 2025 Shontal Biton
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_XG28_RB4401C
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config LOG_BACKEND_SWO_FREQ_HZ
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default 875000
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depends on LOG_BACKEND_SWO
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if SOC_GECKO_USE_RAIL
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config FPU
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default y
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endif # SOC_GECKO_USE_RAIL
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endif # BOARD_XG28_RB4401C
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# Copyright (c) 2025 Shontal Biton
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_XG28_RB4401C
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select SOC_PART_NUMBER_EFR32ZG28B322F1024IM68
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=EFR32ZG28BxxxF1024")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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board_runner_args(openocd)
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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board_runner_args(silabs_commander "--device=EFR32ZG28B322F1024IM68")
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include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake)
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board:
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name: xg28_rb4401c
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full_name: EFR32xG28 868-915 MHz 20 dBm (xG28-RB4401C)
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vendor: silabs
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socs:
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- name: efr32zg28b322f1024im68
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# Copyright (c) 2021 Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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# SPI is implemented via usart so node name isn't spi@...
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list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
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if {[info exists env(OPENOCD_INTERFACE)]} {
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set INTERFACE $env(OPENOCD_INTERFACE)
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} else {
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# By default connect over Debug USB port using the J-Link interface
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set INTERFACE "jlink"
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}
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source [find interface/$INTERFACE.cfg]
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transport select swd
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set CHIPNAME efr32
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source [find target/efm32.cfg]
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$_TARGETNAME configure -event gdb-attach {
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echo "Debugger attaching: halting execution"
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reset halt
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gdb_breakpoint_override hard
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}
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$_TARGETNAME configure -event gdb-detach {
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echo "Debugger detaching: resuming execution"
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resume
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}
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/*
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* Copyright (c) 2025 Shontal Biton
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/pinctrl/silabs/xg28-pinctrl.h>
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&pinctrl {
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usart0_default: usart0_default {
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group0 {
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pins = <USART0_TX_PD11>;
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drive-push-pull;
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output-high;
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};
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group1 {
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pins = <USART0_RX_PD12>;
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input-enable;
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silabs,input-filter;
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};
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};
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};
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/*
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* Copyright (c) 2025 Shontal Biton
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <silabs/efr32zg28b322f1024im68.dtsi>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
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#include "xg28_rb4401c-pinctrl.dtsi"
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/ {
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model = "Silicon Labs BRD4401C";
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compatible = "silabs,xg28_rb4401c", "silabs,efr32zg28";
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chosen {
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zephyr,console = &usart0;
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zephyr,shell-uart = &usart0;
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zephyr,uart-pipe = &usart0;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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};
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aliases {
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led0 = &led0;
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led1 = &led1;
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sw0 = &button0;
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sw1 = &button1;
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watchdog0 = &wdog0;
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};
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
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label = "LED 0";
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};
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led1: led_1 {
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gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
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label = "LED 1";
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};
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
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label = "User Push Button 0";
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zephyr,code = <INPUT_KEY_0>;
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};
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button1: button_1 {
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gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
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label = "User Push Button 1";
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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};
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&cpu0 {
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clock-frequency = <78000000>;
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};
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&pstate_em3 {
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status = "disabled";
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};
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&hfxo {
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status = "okay";
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ctune = <106>;
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precision = <50>;
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};
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&lfxo {
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status = "okay";
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ctune = <38>;
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precision = <50>;
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};
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&hfrcodpll {
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clock-frequency = <DT_FREQ_M(78)>;
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clocks = <&hfxo>;
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dpll-n = <3839>;
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dpll-m = <1919>;
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dpll-edge = "fall";
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dpll-lock = "phase";
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dpll-autorecover;
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};
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&em23grpaclk {
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clocks = <&lfxo>;
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};
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&em4grpaclk {
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clocks = <&lfxo>;
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};
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&sysrtcclk {
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clocks = <&lfxo>;
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};
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&wdog0clk {
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clocks = <&lfxo>;
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};
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&wdog1clk {
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clocks = <&lfxo>;
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};
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&usart0 {
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current-speed = <115200>;
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pinctrl-0 = <&usart0_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&gpio {
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status = "okay";
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};
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&gpioa {
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status = "okay";
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};
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&gpiob {
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status = "okay";
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board-controller-enable {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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};
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&gpioc {
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status = "okay";
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};
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&gpiod {
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status = "okay";
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};
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&wdog0 {
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status = "okay";
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};
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&sysrtc0 {
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status = "okay";
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};
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&se {
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status = "okay";
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};
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&dcdc {
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status = "okay";
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regulator-boot-on;
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regulator-initial-mode = <SILABS_DCDC_MODE_BUCK>;
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silabs,pfmx-peak-current-milliamp = <80>;
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Reserve 48 kB for the bootloader */
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(48)>;
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read-only;
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};
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/* Reserve 208 kB for the application in slot 0 */
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slot0_partition: partition@c000 {
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label = "image-0";
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reg = <0x0000c000 DT_SIZE_K(208)>;
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};
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/* Reserve 208 kB for the application in slot 1 */
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slot1_partition: partition@40000 {
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label = "image-1";
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reg = <0x00040000 DT_SIZE_K(208)>;
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};
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/* Reserve 32 kB for the scratch partition */
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scratch_partition: partition@74000 {
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label = "image-scratch";
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reg = <0x00074000 DT_SIZE_K(32)>;
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};
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/* Set 16 kB of storage at the end of the 1536 kB of flash */
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storage_partition: partition@7c000 {
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label = "storage";
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reg = <0x0007c000 DT_SIZE_K(16)>;
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};
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};
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};
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identifier: xg28_rb4401c
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name: EFR32xG28 868-915 MHz 20 dBm Radio Board (xG28-RB4401C, BRD4401C)
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type: mcu
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arch: arm
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ram: 256
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flash: 1024
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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supported:
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- bluetooth
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- gpio
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- uart
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- watchdog
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testing:
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ignore_tags:
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- pm
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- hwinfo
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vendor: silabs
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_ARM_MPU=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_GPIO=y
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CONFIG_SOC_GECKO_EMU_DCDC=y
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CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y

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