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ZhaoQiang-b45475ZhaoQiang-b45475
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drivers: adc: add support sar adc driver
Add driver for the SAR ADC Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
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‎drivers/adc/CMakeLists.txt

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@@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_mcux_12b1msps_sar.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_LPADC adc_mcux_lpadc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_SAR_ADC adc_mcux_sar_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_VF610 adc_vf610.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)

‎drivers/adc/Kconfig.mcux

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@@ -37,6 +37,14 @@ config ADC_MCUX_LPADC
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help
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Enable the MCUX LPADC driver.
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config ADC_MCUX_SAR_ADC
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bool "MCUX SAR ADC driver"
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default y
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select ADC_CONFIGURABLE_INPUTS
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depends on DT_HAS_NXP_SAR_ADC_ENABLED
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help
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Enable the MCUX SAR ADC driver.
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if ADC_MCUX_12B1MSPS_SAR || ADC_MCUX_LPADC
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config ADC_MCUX_ETC
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bool "MCUX ADC ETC driver"
@@ -123,3 +131,18 @@ config LPADC_CHANNEL_COUNT
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endif # ADC_MCUX_LPADC
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if ADC_MCUX_SAR_ADC
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config SAR_ADC_CHANNEL_COUNT
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int "SAR_ADC channel count"
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default 8
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range 1 8
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help
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Amount of hardware command channels to use, reduce to save RAM.
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The user can reduce this value if their application uses fewer than
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8 ADC channels. This value corresponds to how many of the CMD
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registers can be configured within the ADC.
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endif # ADC_MCUX_SAR_ADC

‎drivers/adc/adc_mcux_sar_adc.c

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/*
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* Copyright 2025 NXP
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*
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* Based on adc_mcux_sar_adc.c, which is:
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* Copyright 2023-2024 NXP
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* Copyright (c) 2020 Toby Firth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_sar_adc
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#include <errno.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <fsl_sar_adc.h>
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LOG_MODULE_REGISTER(adc_mcux_sar_adc);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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struct mcux_sar_adc_config {
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ADC_Type *base;
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void (*irq_config_func)(const struct device *dev);
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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};
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struct mcux_sar_adc_data {
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const struct device *dev;
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struct adc_context ctx;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint32_t channels;
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};
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static int mcux_sar_adc_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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/* User may configure maximum number of active channels */
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if (channel_cfg->channel_id >= CONFIG_SAR_ADC_CHANNEL_COUNT) {
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LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
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return -EINVAL;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Unsupported channel acquisition time");
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return -ENOTSUP;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
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return -ENOTSUP;
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}
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if (channel_cfg->reference != ADC_REF_INTERNAL) {
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LOG_ERR("Unsupported channel reference");
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return -ENOTSUP;
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}
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return 0;
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}
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static int mcux_sar_adc_start_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct mcux_sar_adc_config *config = dev->config;
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struct mcux_sar_adc_data *data = dev->data;
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ADC_Type *base = config->base;
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uint8_t channel_id;
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if (sequence->resolution != 12) {
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LOG_ERR("Unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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channel_id = CONFIG_SAR_ADC_CHANNEL_COUNT;
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while (channel_id-- > 0) {
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if (sequence->channels & BIT(channel_id)) {
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ADC_EnableSpecificChannelNormalConv(base, channel_id);
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} else {
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ADC_DisableSpecificChannelNormalConv(base, channel_id);
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}
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}
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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int error = adc_context_wait_for_completion(&data->ctx);
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return error;
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}
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static int mcux_sar_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct mcux_sar_adc_data *data = dev->data;
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int error;
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adc_context_lock(&data->ctx, async ? true : false, async);
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error = mcux_sar_adc_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int mcux_sar_adc_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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return mcux_sar_adc_read_async(dev, sequence, NULL);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct mcux_sar_adc_data *data = CONTAINER_OF(ctx, struct mcux_sar_adc_data, ctx);
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const struct mcux_sar_adc_config *config = data->dev->config;
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ADC_Type *base = config->base;
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data->channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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ADC_StartConvChain(base, kADC_NormalConvOneShotMode);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct mcux_sar_adc_data *data = CONTAINER_OF(ctx, struct mcux_sar_adc_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static void mcux_sar_adc_isr(const struct device *dev)
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{
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const struct mcux_sar_adc_config *config = dev->config;
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struct mcux_sar_adc_data *data = dev->data;
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ADC_Type *base = config->base;
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adc_conv_result_t conv_result;
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uint16_t channel_id;
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if (((ADC_GetConvIntStatus(base) & kADC_NormalConvChainEndIntFlag))) {
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ADC_ClearConvIntStatus(base, kADC_NormalConvChainEndIntFlag);
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}
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for (channel_id = 0; channel_id < CONFIG_SAR_ADC_CHANNEL_COUNT; channel_id++) {
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if (ADC_GetChannelConvResult(base, &conv_result, channel_id)) {
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data->channels &= ~BIT(channel_id);
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*(data->buffer++) = conv_result.convData;
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if (data->channels == 0) {
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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}
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}
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static int mcux_sar_adc_init(const struct device *dev)
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{
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const struct mcux_sar_adc_config *config = dev->config;
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struct mcux_sar_adc_data *data = dev->data;
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ADC_Type *base = config->base;
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adc_config_t adc_config;
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adc_calibration_config_t calibrationConfig;
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ADC_GetDefaultConfig(&adc_config);
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ADC_Init(base, &adc_config);
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ADC_SetConvMode(base, kADC_NormalConvOneShotMode);
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ADC_EnableConvInt(base, (uint32_t)kADC_NormalConvChainEndIntEnable);
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/* Do calibration to reduce or eliminate the various error contribution effects. */
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calibrationConfig.enableAverage = true;
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calibrationConfig.sampleTime = kADC_SampleTime22;
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#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG == 1U))
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calibrationConfig.averageSampleNumbers = kADC_AverageSampleNumbers32;
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#else
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calibrationConfig.averageSampleNumbers = kADC_AverageSampleNumbers512;
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#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */
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if (!(ADC_DoCalibration(base, &calibrationConfig))) {
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LOG_WRN("Calibration failed.");
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}
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config->irq_config_func(dev);
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data->dev = dev;
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static DEVICE_API(adc, mcux_sar_adc_driver_api) = {
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.channel_setup = mcux_sar_adc_channel_setup,
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.read = mcux_sar_adc_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = mcux_sar_adc_read_async,
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#endif
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};
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#define SAR_ADC_MCUX_INIT(n) \
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\
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static void mcux_sar_adc_config_func_##n(const struct device *dev); \
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\
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static const struct mcux_sar_adc_config mcux_sar_adc_config_##n = { \
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.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
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.irq_config_func = mcux_sar_adc_config_func_##n, \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
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}; \
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static struct mcux_sar_adc_data mcux_sar_adc_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(mcux_sar_adc_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(mcux_sar_adc_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(mcux_sar_adc_data_##n, ctx), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &mcux_sar_adc_init, NULL, &mcux_sar_adc_data_##n, \
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&mcux_sar_adc_config_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
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&mcux_sar_adc_driver_api); \
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\
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static void mcux_sar_adc_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_sar_adc_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(SAR_ADC_MCUX_INIT)

‎dts/bindings/adc/nxp,sar-adc.yaml

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP SAR ADC controller
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compatible: "nxp,sar-adc"
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include: [adc-controller.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#io-channel-cells":
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const: 1
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io-channel-cells:
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- input

‎modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

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@@ -15,6 +15,7 @@ endif()
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set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 CONFIG_MCUX_COMPONENT_driver.src_2)
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set_variable_ifdef(CONFIG_GPIO_MCUX_IGPIO CONFIG_MCUX_COMPONENT_driver.igpio)
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set_variable_ifdef(CONFIG_ADC_MCUX_LPADC CONFIG_MCUX_COMPONENT_driver.lpadc)
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set_variable_ifdef(CONFIG_ADC_MCUX_SAR_ADC CONFIG_MCUX_COMPONENT_driver.sar_adc)
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set_variable_ifdef(CONFIG_COUNTER_MCUX_CTIMER CONFIG_MCUX_COMPONENT_driver.ctimer)
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set_variable_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC CONFIG_MCUX_COMPONENT_driver.lpc_rtc)
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set_variable_ifdef(CONFIG_GLIKEY_MCUX_GLIKEY CONFIG_MCUX_COMPONENT_driver.glikey)

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