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lines changed Original file line number Diff line number Diff line change 37
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};
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};
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+ &dma0 {
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+ status = "okay";
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+ };
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+
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+ &dma1 {
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+ status = "okay";
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+ };
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+
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+ &dma2 {
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+ status = "okay";
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+ };
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+
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&flx3 {
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mchp,flexcom-mode = <SAM_FLEXCOM_MODE_USART>;
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status = "okay";
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#clock-cells = <1>;
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};
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+ dma0: dma-controller@e2808000 {
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+ compatible = "atmel,sam-xdmac";
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+ reg = <0xe2808000 0x1000>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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+ #dma-cells = <2>;
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+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
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+ clock-names = "dma_clk";
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+ status = "disabled";
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+ };
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+
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+ dma1: dma-controller@e280c000 {
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+ compatible = "atmel,sam-xdmac";
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+ reg = <0xe280c000 0x1000>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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+ #dma-cells = <2>;
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+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
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+ clock-names = "dma_clk";
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+ status = "disabled";
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+ };
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+
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+ dma2: dma-controller@e1200000 {
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+ compatible = "atmel,sam-xdmac";
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+ reg = <0xe1200000 0x1000>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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+ #dma-cells = <2>;
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+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
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+ clock-names = "dma_clk";
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+ status = "disabled";
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+ };
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+
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flx0: flexcom@e1818000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe1818000 0x200>;
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