drivers: gpio: Update gpio and pinctrl driver for support RX261

Update gpio driver and pinctrl driver for support RX261

Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>

Author: Phi Tran

drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c

@@ -16,7 +16,9 @@
 
 extern const uint8_t g_gpio_open_drain_n_support[];
 extern const uint8_t g_gpio_pull_up_support[];
+#ifndef CONFIG_SOC_SERIES_RX261
 extern const uint8_t g_gpio_dscr_support[];
+#endif
 
 static bool gpio_pin_function_check(uint8_t const *check_array, uint8_t port_number,
 				    uint8_t pin_number)
@@ -45,6 +47,7 @@ static int pinctrl_configure_pullup(const pinctrl_soc_pin_t *pin, uint32_t value
 	return ret;
 }
 
+#ifndef CONFIG_SOC_SERIES_RX261
 static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value)
 {
 	gpio_port_pin_t port_pin;
@@ -61,6 +64,7 @@ static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value)
 
 	return ret;
 }
+#endif
 
 static int pinctrl_configure_opendrain(const pinctrl_soc_pin_t *pin, uint32_t value)
 {
@@ -124,13 +128,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
 		if (ret != 0) {
 			return -EINVAL;
 		}
-
+#ifndef CONFIG_SOC_SERIES_RX261
 		/* Set drive-strength */
 		ret = pinctrl_configure_dscr(pin, pin->cfg.drive_strength);
 
 		if (ret != 0) {
 			return -EINVAL;
 		}
+#endif
 
 		/* Set pin function */
 		pconfig.analog_enable = pin->cfg.analog_enable;

include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h

@@ -16,10 +16,14 @@
 #define RX_PSEL_MASK 0x1f
 #define RX_PSEL_POS  9
 
-#define RX_PSEL_SCI_1 0xA
-#define RX_PSEL_SCI_6 0xB
-#define RX_PSEL_TMR   0x5
-#define RX_PSEL_POE   0x7
+#define RX_PSEL_RSCI      0xA
+#define RX_PSEL_RSCI_TXDB 0xC
+#define RX_PSEL_SCI_1     0xA
+#define RX_PSEL_SCI_5     0xA
+#define RX_PSEL_SCI_6     0xB
+#define RX_PSEL_SCI_12    0xC
+#define RX_PSEL_TMR       0x5
+#define RX_PSEL_POE       0x7
 
 /* P0nPFS */
 #define RX_PSEL_P0nPFS_HIZ    0x0