spi_nxp_lpspi: Remove call to MasterInit

For optimization purpose, remove calls to SDK. Since we know exactly
what we want, this results in smaller code size.

Also, this code calculates the SCK parameters more efficiently than the
SDK driver did it by using a binary (instead of linear) search.

Lastly, remove call to LPSPI_Reset in the init call and replace with
native driver code, and remove inclusion of SDK header.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>

Author: decsny

drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c

@@ -15,7 +15,9 @@
 LOG_MODULE_REGISTER(spi_lpspi, CONFIG_SPI_LOG_LEVEL);
 
 #include "spi_nxp_lpspi_priv.h"
-#include <fsl_lpspi.h>
+
+/* simple macro for readability of the equations used in the clock configuring */
+#define TWO_EXP(power) BIT(power)
 
 #if defined(LPSPI_RSTS) || defined(LPSPI_CLOCKS)
 static LPSPI_Type *const lpspi_bases[] = LPSPI_BASE_PTRS;
@@ -116,6 +118,156 @@ static inline int lpspi_validate_xfer_args(const struct spi_config *spi_cfg)
 	return 0;
 }
 
+static uint8_t lpspi_calc_delay(uint32_t desired_delay_ns, uint32_t best_delay_ns,
+				uint32_t prescaled_clock, uint32_t additional_scaler)
+{
+	uint64_t real_delay = NSEC_PER_SEC / prescaled_clock;
+	uint8_t best_scaler = 0, scaler = 0;
+	uint32_t diff, min_diff = 0xFFFFFFFF;
+
+	while (scaler < 256 && min_diff != 0) {
+		real_delay *= ((uint64_t)scaler + 1 + (uint64_t)additional_scaler);
+
+		/* Delay must not be less than desired */
+		if (real_delay >= desired_delay_ns) {
+			diff = (uint32_t)(real_delay - (uint64_t)desired_delay_ns);
+			if (min_diff > diff) {
+				/* a better match found */
+				min_diff = diff;
+				best_scaler = scaler;
+			}
+		}
+
+		scaler++;
+	}
+
+	return best_scaler;
+}
+
+static inline void lpspi_set_delays(const struct device *dev, uint32_t prescaled_clock)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	uint64_t minimum_delay_ns = NSEC_PER_SEC / prescaled_clock;
+	const struct lpspi_config *config = dev->config;
+	uint32_t ccr = base->CCR;
+
+	ccr &= ~(LPSPI_CCR_PCSSCK_MASK | LPSPI_CCR_SCKPCS_MASK | LPSPI_CCR_DBT_MASK);
+
+	if (config->pcs_sck_delay <= minimum_delay_ns) {
+		ccr |= LPSPI_CCR_PCSSCK(lpspi_calc_delay(config->pcs_sck_delay,
+							 minimum_delay_ns * 256,
+							 prescaled_clock, 0));
+	}
+
+	if (config->sck_pcs_delay <= minimum_delay_ns) {
+		ccr |= LPSPI_CCR_SCKPCS(lpspi_calc_delay(config->sck_pcs_delay,
+							 minimum_delay_ns * 256,
+							 prescaled_clock, 0));
+	}
+
+	if (config->transfer_delay <= (2 * minimum_delay_ns)) {
+		ccr |= LPSPI_CCR_DBT(lpspi_calc_delay(config->transfer_delay,
+						      minimum_delay_ns * 257,
+						      prescaled_clock, 1));
+	}
+
+	base->CCR = ccr;
+}
+
+
+/* This function configures the clock control register (CCR) for the desired frequency
+ * It does a binary search for the optimal CCR divider and TCR prescaler.
+ * The return value is the actual best frequency found, and the prescale_value parameter
+ * is changed to the best value of the prescaler, for use in setting the TCR outside this function.
+ */
+static inline uint32_t lpspi_set_sckdiv(LPSPI_Type *base, uint32_t desired_freq,
+					uint32_t clock_freq, uint8_t *prescale_value)
+{
+	uint8_t best_prescaler = 0, best_div = 0;
+	uint32_t best_freq = 0;
+
+	for (uint8_t prescaler = 0U; prescaler < 8U; prescaler++) {
+		uint8_t high = 255, low = 0, div = 255;
+		uint32_t real_freq = 0;
+
+		/* maximum freq won't get better than what we got with previous prescaler */
+		if (clock_freq / (TWO_EXP(prescaler) * 2) < best_freq) {
+			goto done;
+		}
+
+		while (div > 0) {
+			div = low + (high - low) / 2;
+			real_freq = (clock_freq / (TWO_EXP(prescaler) * (div + 2)));
+
+			/* ensure that we do not exceed desired freq */
+			if (real_freq > desired_freq) {
+				low = div + 1;
+				continue;
+			} else {
+				high = div - 1;
+			}
+
+			/* check if we are closer to the desired */
+			if (real_freq >= best_freq) {
+				best_prescaler = prescaler;
+				best_div = div;
+				best_freq = real_freq;
+			}
+
+			/* if our best found is a match, we're done */
+			if (best_freq == desired_freq) {
+				goto done;
+			}
+		}
+	}
+
+done:
+	uint32_t ccr_val = base->CCR & ~LPSPI_CCR_SCKDIV_MASK;
+
+	ccr_val |= LPSPI_CCR_SCKDIV(best_div);
+
+	base->CCR = ccr_val;
+
+	*prescale_value = best_prescaler;
+
+	return best_freq;
+}
+
+/* This function configures everything except the TCR and the clock scaler */
+static void lpspi_basic_config(const struct device *dev, const struct spi_config *spi_cfg)
+{
+	const struct lpspi_config *config = dev->config;
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	uint32_t pcs_control_bit = 1 << (LPSPI_CFGR1_PCSPOL_SHIFT + spi_cfg->slave);
+	uint32_t cfgr1_val = 0;
+
+	if (spi_cfg->operation & SPI_CS_ACTIVE_HIGH) {
+		cfgr1_val |= pcs_control_bit;
+	} else {
+		cfgr1_val &= ~pcs_control_bit;
+	}
+
+	if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) {
+		cfgr1_val |= LPSPI_CFGR1_MASTER_MASK;
+	}
+
+	if (config->tristate_output) {
+		cfgr1_val |= LPSPI_CFGR1_OUTCFG_MASK;
+	}
+
+	cfgr1_val |= config->data_pin_config << LPSPI_CFGR1_PINCFG_SHIFT;
+
+	base->CFGR1 = cfgr1_val;
+
+	if (IS_ENABLED(CONFIG_DEBUG)) {
+		/* DEBUG mode makes it so the lpspi does not keep
+		 * running while debugger has halted the chip.
+		 * This makes debugging spi transfers easier.
+		 */
+		base->CR |= LPSPI_CR_DBGEN_MASK;
+	}
+}
+
 int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cfg)
 {
 	const struct lpspi_config *config = dev->config;
@@ -124,8 +276,8 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
 	bool already_configured = spi_context_configured(ctx, spi_cfg);
 	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
 	uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
-	lpspi_master_config_t master_config;
 	uint32_t clock_freq;
+	uint8_t prescaler;
 	int ret;
 
 	/* fast path to avoid reconfigure */
@@ -141,10 +293,8 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
 		return ret;
 	}
 
-	ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq);
-	if (ret) {
-		return ret;
-	}
+	/* For the purpose of configuring the LPSPI, 8 is the minimum frame size for the hardware */
+	word_size = word_size < 8 ? 8 : word_size;
 
 	/* specific driver implementation should set up watermarks and interrupts.
 	 * we reset them here to avoid any unexpected events during configuring.
@@ -164,35 +314,26 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
 
 	data->ctx.config = spi_cfg;
 
-	LPSPI_MasterGetDefaultConfig(&master_config);
-
-	master_config.bitsPerFrame = word_size < 8 ? 8 : word_size; /* minimum FRAMSZ is 8 */
-	master_config.cpol = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
-				     ? kLPSPI_ClockPolarityActiveLow
-				     : kLPSPI_ClockPolarityActiveHigh;
-	master_config.cpha = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
-				     ? kLPSPI_ClockPhaseSecondEdge
-				     : kLPSPI_ClockPhaseFirstEdge;
-	master_config.direction =
-		(spi_cfg->operation & SPI_TRANSFER_LSB) ? kLPSPI_LsbFirst : kLPSPI_MsbFirst;
-	master_config.baudRate = spi_cfg->frequency;
-	master_config.pcsToSckDelayInNanoSec = config->pcs_sck_delay;
-	master_config.lastSckToPcsDelayInNanoSec = config->sck_pcs_delay;
-	master_config.betweenTransferDelayInNanoSec = config->transfer_delay;
-	master_config.whichPcs = spi_cfg->slave + kLPSPI_Pcs0;
-	master_config.pcsActiveHighOrLow = (spi_cfg->operation & SPI_CS_ACTIVE_HIGH)
-				    ? kLPSPI_PcsActiveHigh : kLPSPI_PcsActiveLow;
-	master_config.pinCfg = config->data_pin_config;
-	master_config.dataOutConfig = config->tristate_output ? kLpspiDataOutTristate :
-								kLpspiDataOutRetained;
-
-	LPSPI_MasterInit(base, &master_config, clock_freq);
-	LPSPI_SetDummyData(base, 0);
+	lpspi_basic_config(dev, spi_cfg);
 
-	if (IS_ENABLED(CONFIG_DEBUG)) {
-		base->CR |= LPSPI_CR_DBGEN_MASK;
+	ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq);
+	if (ret) {
+		return ret;
 	}
 
+	lpspi_set_sckdiv(base, spi_cfg->frequency, clock_freq, &prescaler);
+	lpspi_set_delays(dev, clock_freq / TWO_EXP(prescaler));
+
+	base->CR |= LPSPI_CR_MEN_MASK;
+
+	base->TCR = LPSPI_TCR_CPOL(!!(spi_cfg->operation & SPI_MODE_CPOL)) |
+		    LPSPI_TCR_CPHA(!!(spi_cfg->operation & SPI_MODE_CPHA)) |
+		    LPSPI_TCR_LSBF(!!(spi_cfg->operation & SPI_TRANSFER_LSB)) |
+		    LPSPI_TCR_FRAMESZ(SPI_WORD_SIZE_GET(spi_cfg->operation)) |
+		    LPSPI_TCR_PRESCALE(prescaler) | LPSPI_TCR_PCS(spi_cfg->slave);
+
+	lpspi_wait_tx_fifo_empty(dev);
+
 	return 0;
 }
 
@@ -235,7 +376,10 @@ int spi_nxp_init_common(const struct device *dev)
 		return err;
 	}
 
-	LPSPI_Reset(base);
+	/* Full software reset */
+	base->CR |= LPSPI_CR_RST_MASK;
+	base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
+	base->CR = 0x00U;
 
 	config->irq_config_func(dev);