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15 | 15 | #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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16 | 16 | #include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
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17 | 17 | #include <zephyr/dt-bindings/gpio/gpio.h>
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| 18 | +#include <zephyr/dt-bindings/video/video-interfaces.h> |
18 | 19 | #include <freq.h>
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19 | 20 |
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20 | 21 | / {
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643 | 644 | status = "disabled";
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644 | 645 | };
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645 | 646 |
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| 647 | + dcmipp: dcmipp@58002000 { |
| 648 | + compatible = "st,stm32n6-dcmipp", "st,stm32-dcmipp"; |
| 649 | + reg = <0x58002000 0x1000>; |
| 650 | + clock-names = "dcmipp", "dcmipp-ker", "csi"; |
| 651 | + clocks = <&rcc STM32_CLOCK(APB5, 2)>, |
| 652 | + <&rcc STM32_SRC_IC17 DCMIPP_SEL(2)>, |
| 653 | + <&rcc STM32_CLOCK(APB5, 6)>; |
| 654 | + interrupts = <48 0>; |
| 655 | + resets = <&rctl STM32_RESET(APB5, 2)>, |
| 656 | + <&rctl STM32_RESET(APB5, 6)>; |
| 657 | + status = "disabled"; |
| 658 | + |
| 659 | + ports { |
| 660 | + #address-cells = <1>; |
| 661 | + #size-cells = <0>; |
| 662 | + |
| 663 | + port@0 { |
| 664 | + reg = <0>; |
| 665 | + |
| 666 | + endpoint { |
| 667 | + remote-endpoint-label = ""; |
| 668 | + bus-type = <VIDEO_BUS_TYPE_CSI2_DPHY>; |
| 669 | + }; |
| 670 | + }; |
| 671 | + |
| 672 | + port@1 { |
| 673 | + #address-cells = <1>; |
| 674 | + #size-cells = <0>; |
| 675 | + |
| 676 | + reg = <1>; |
| 677 | + |
| 678 | + dcmipp_pipe_dump: endpoint@0 { |
| 679 | + compatible = "st,stm32-dcmipp-pipe"; |
| 680 | + reg = <0>; |
| 681 | + }; |
| 682 | + |
| 683 | + dcmipp_pipe_main: endpoint@1 { |
| 684 | + compatible = "st,stm32-dcmipp-pipe"; |
| 685 | + reg = <1>; |
| 686 | + }; |
| 687 | + |
| 688 | + dcmipp_pipe_aux: endpoint@2 { |
| 689 | + compatible = "st,stm32-dcmipp-pipe"; |
| 690 | + reg = <2>; |
| 691 | + }; |
| 692 | + }; |
| 693 | + }; |
| 694 | + }; |
| 695 | + |
646 | 696 | ethernet@58036000 {
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647 | 697 | reg = <0x58036000 0x8000>;
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648 | 698 | compatible = "st,stm32-ethernet-controller";
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