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soc: add wch/ch32v307
dts: add riscv/wch/ch32v307 and packages wch has provide a ch32v307 soc series Signed-off-by: Thomas Boje <info@andocs.biz>
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‎dts/bindings/vendor-prefixes.txt

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@@ -595,6 +595,7 @@ sandisk Sandisk Corporation
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satoz Satoz International Co., Ltd
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sbs Smart Battery System
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sc Space Cubics, LLC
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scdz Shenzhen Qiushi IoT Technology Co., Ltd.
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schindler Schindler
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sciosense Sciosense B.V.
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seagate Seagate Technology PLC

‎dts/riscv/wch/ch32v307/ch32v307.dtsi

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/*
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* Copyright (c) 2025 Thomas Boje
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <mem.h>
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#include <wch/qingke-v4f.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "wch,ch32v00x-hse-clock";
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clock-frequency = <DT_FREQ_M(32)>;
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "wch,ch32v00x-hsi-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "wch,ch32v20x_30x-pll-clock";
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mul = <18>;
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status = "disabled";
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};
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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flash: flash-controller@40022000 {
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compatible = "wch,ch32v20x_30x-flash-controller";
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reg = <0x40022000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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reg = <0x08000000 DT_SIZE_K(480)>;
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};
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};
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pwr: pwr@40007000 {
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compatible = "wch,pwr";
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reg = <0x40007000 16>;
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};
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pinctrl: pin-controller@40010000 {
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compatible = "wch,20x_30x-afio";
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reg = <0x40010000 16>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>;
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gpioa: gpio@40010800 {
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compatible = "wch,gpio";
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reg = <0x40010800 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
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};
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gpiob: gpio@40010C00 {
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compatible = "wch,gpio";
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reg = <0x40010C00 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
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};
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gpioc: gpio@40011000 {
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compatible = "wch,gpio";
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reg = <0x40011000 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
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};
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gpiod: gpio@40011400 {
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compatible = "wch,gpio";
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reg = <0x40011400 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
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};
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gpioe: gpio@40011800 {
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compatible = "wch,gpio";
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reg = <0x40011800 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_IOPE>;
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};
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};
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usart1: uart@40013800 {
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compatible = "wch,usart";
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reg = <0x40013800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
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interrupt-parent = <&pfic>;
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interrupts = <53>;
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status = "disabled";
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};
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usart2: uart@40004400 {
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compatible = "wch,usart";
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reg = <0x40004400 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
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interrupt-parent = <&pfic>;
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interrupts = <54>;
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status = "disabled";
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};
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usart3: uart@40004800 {
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compatible = "wch,usart";
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reg = <0x40004800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
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interrupt-parent = <&pfic>;
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interrupts = <55>;
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status = "disabled";
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};
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usart4: uart@40004c00 {
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compatible = "wch,usart";
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reg = <0x40004C00 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
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interrupt-parent = <&pfic>;
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interrupts = <68>;
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status = "disabled";
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};
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usart5: uart@40005000 {
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compatible = "wch,usart";
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reg = <0x40005000 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART5>;
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interrupt-parent = <&pfic>;
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interrupts = <69>;
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status = "disabled";
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};
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usart6: uart@40001800 {
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compatible = "wch,usart";
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reg = <0x40001800 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART6>;
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interrupt-parent = <&pfic>;
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interrupts = <87>;
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status = "disabled";
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};
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usart7: uart@40001c00 {
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compatible = "wch,usart";
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reg = <0x40001c00 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART7>;
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interrupt-parent = <&pfic>;
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interrupts = <88>;
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status = "disabled";
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};
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usart8: uart@40002000 {
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compatible = "wch,usart";
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reg = <0x40002000 0x20>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_USART8>;
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interrupt-parent = <&pfic>;
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interrupts = <89>;
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status = "disabled";
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};
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rcc: rcc@40021000 {
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compatible = "wch,rcc";
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reg = <0x40021000 16>;
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#clock-cells = <1>;
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status = "okay";
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};
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dma1: dma@40020000 {
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compatible = "wch,wch-dma";
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reg = <0x40020000 0x90>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>;
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#dma-cells = <1>;
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interrupt-parent = <&pfic>;
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interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>;
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dma-channels = <7>;
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};
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dma2: dma@40020400 {
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compatible = "wch,wch-dma";
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reg = <0x40020400 0x90>;
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clocks = <&rcc CH32V20X_V30X_CLOCK_DMA2>;
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#dma-cells = <1>;
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interrupt-parent = <&pfic>;
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interrupts = <72>, <73>, <74>, <75>, <76>, <98>, <99>, <100>,
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<101>, <102>, <103>;
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dma-channels = <11>;
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};
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};
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};
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&cpu0 {
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clock-frequency = <DT_FREQ_M(127)>;
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};

‎dts/riscv/wch/ch32v307/ch32v307rc.dtsi

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/*
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* Copyright (c) 2025 Thomas Boje
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v307/ch32v307.dtsi>
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&gpiod {
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gpio-reserved-ranges = <3 13>;
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};
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&gpioe {
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gpio-reserved-ranges = <0 16>;
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};

‎dts/riscv/wch/ch32v307/ch32v307vc.dtsi

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/*
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* Copyright (c) 2025 Thomas Boje
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v307/ch32v307.dtsi>
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‎dts/riscv/wch/ch32v307/ch32v307wc.dtsi

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/*
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* Copyright (c) 2025 Thomas Boje
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <wch/ch32v307/ch32v307.dtsi>
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&gpiod {
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gpio-reserved-ranges = <3 5>, <10 6>;
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};
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&gpioe {
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gpio-reserved-ranges = <1 15>;
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};

‎soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v307

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# Copyright (c) 2025 Thomas Boje
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# SPDX-License-Identifier: Apache-2.0
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if SOC_CH32V307
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config VECTOR_TABLE_SIZE
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default 103
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config NUM_IRQS
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default 128
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endif # SOC_CH32V307

‎soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v307

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# Copyright (c) 2025 Thomas Boje
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# SPDX-License-Identifier: Apache-2.0
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config SOC_CH32V307
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bool
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select SOC_SERIES_QINGKE_V4F
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config SOC
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default "ch32v307" if SOC_CH32V307

‎soc/wch/ch32v/qingke_v4f/vector.S

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SECTION_FUNC(vectors, ivt)
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.option norvc
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#ifndef SOC_CH32V307
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/* Jump to 0x08000008, into the main flash zone where j __start is */
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lui x5, 0x8000
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jr 0x8(x5)
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#endif // SOC_CH32V307
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j __start
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.rept CONFIG_VECTOR_TABLE_SIZE
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.word _isr_wrapper

‎soc/wch/ch32v/soc.yml

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# Copyright (c) 2024 Michael Hope
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# Copyright (c) 2025 Thomas Boje
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# SPDX-License-Identifier: Apache-2.0
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family:
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- name: qingke-v4f
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socs:
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- name: ch32v303
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- name: ch32v307

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