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soc: Add support for Silabs EFM32TG
* ARM Cortex-M3 processor * Up to 32 kB Flash and 4 kB RAM memory * Energy efficient and autonomous peripherals * Ultra low power Energy Modes * Fast wake-up Signed-off-by: Lukas Woodtli <woodtli.lukas@gmail.com>
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‎dts/arm/silabs/efm32tg.dtsi

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/*
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* Copyright (c) 2025 Lukas Woodtli
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include "gpio_gecko.h"
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/ {
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chosen {
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zephyr,flash-controller = &msc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m3";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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msc: flash-controller@400c0000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x400c0000 0x78>;
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interrupts = <21 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <4>;
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erase-block-size = <512>;
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};
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};
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usart0: usart@4000c000 { /* USART0 */
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compatible = "silabs,gecko-usart";
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reg = <0x4000c000 0x400>;
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interrupts = <3 0>, <4 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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status = "disabled";
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};
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usart1: usart@4000c400 { /* USART1 */
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compatible = "silabs,gecko-usart";
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reg = <0x4000c400 0x400>;
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interrupts = <15 0>, <16 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <1>;
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status = "disabled";
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};
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leuart0: leuart@40084000 { /* LEUART0 */
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compatible = "silabs,gecko-leuart";
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reg = <0x40084000 0x400>;
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interrupts = <24 0>;
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peripheral-id = <0>;
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status = "disabled";
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};
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leuart1: leuart@40084400 { /* LEUART1 */
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compatible = "silabs,gecko-leuart";
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reg = <0x40084400 0x400>;
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interrupts = <25 0>;
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peripheral-id = <1>;
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status = "disabled";
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};
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i2c0: i2c@4000a000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4000a000 0x400>;
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interrupts = <9 0>;
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status = "disabled";
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};
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gpio@40006100 {
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compatible = "silabs,gecko-gpio";
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reg = <0x40006100 0xf00>;
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interrupts = <1 2 11 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@40006000 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40006000 0x24>;
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peripheral-id = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@40006024 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40006024 0x24>;
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peripheral-id = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@40006048 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40006048 0x24>;
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peripheral-id = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiod: gpio@4000606c {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x4000606c 0x24>;
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peripheral-id = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioe: gpio@40006090 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x40006090 0x24>;
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peripheral-id = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiof: gpio@400060b4 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x400060b4 0x24>;
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peripheral-id = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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pinctrl: pin-controller {
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/* Pin controller is a "virtual" device since SiLabs SoCs do pin
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* control in a distributed way (GPIO registers and PSEL
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* registers on each peripheral).
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*/
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compatible = "silabs,gecko-pinctrl";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};

‎modules/hal_silabs/gecko/CMakeLists.txt

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@@ -102,6 +102,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_TIMER ${EMLIB_DIR}/src/em_t
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zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_USART ${EMLIB_DIR}/src/em_usart.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_WDOG ${EMLIB_DIR}/src/em_wdog.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_EFM32WG ${DEVICE_DIR}/SiliconLabs/EFM32WG/Source/system_efm32wg.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_EFM32TG ${DEVICE_DIR}/SiliconLabs/EFM32TG/Source/system_efm32tg.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_EFR32BG13P ${DEVICE_DIR}/SiliconLabs/EFR32BG13P/Source/system_efr32bg13p.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG1P ${DEVICE_DIR}/SiliconLabs/EFR32FG1P/Source/system_efr32fg1p.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG13P ${DEVICE_DIR}/SiliconLabs/EFR32FG13P/Source/system_efr32fg13p.c)

‎soc/silabs/silabs_s0/efm32tg/Kconfig

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# Copyright (c) 2025 Lukas Woodtli
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_EFM32TG
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select ARM
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select CPU_CORTEX_M3
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select CPU_CORTEX_M_HAS_DWT
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select HAS_SILABS_GECKO
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select SOC_GECKO_CMU
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select SOC_GECKO_GPIO
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select HAS_PM
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config SOC_GECKO_SDID
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default 73 if SOC_SERIES_EFM32TG

‎soc/silabs/silabs_s0/efm32tg/Kconfig.defconfig

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# Copyright (c) 2025 Lukas Woodtli
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_EFM32TG
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config NUM_IRQS
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# must be >= the highest interrupt number used
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default 39
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endif

‎soc/silabs/silabs_s0/efm32tg/Kconfig.soc

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# Copyright (c) 2025 Lukas Woodtli
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_EFM32TG
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bool
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select SOC_FAMILY_SILABS_S0
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help
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Silicon Labs EFM32TG (Tiny Gecko) Series MCU
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config SOC_PART_NUMBER_EFM32TG840F32
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bool
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select SOC_SERIES_EFM32TG
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config SOC_SERIES
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default "efm32tg" if SOC_SERIES_EFM32TG
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config SOC
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default "efm32tg840f32" if SOC_PART_NUMBER_EFM32TG840F32
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config SOC_PART_NUMBER
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default "EFM32TG840F32" if SOC_PART_NUMBER_EFM32TG840F32

‎soc/silabs/silabs_s0/efm32tg/soc.h

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/*
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* Copyright (c) 2025 Lukas Woodtli
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Board configuration macros for the efm32tg soc
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*
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#include <zephyr/sys/util.h>
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#ifndef _ASMLANGUAGE
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#include <em_bus.h>
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#include <em_common.h>
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#include "soc_pinmap.h"
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#include "../common/soc_gpio.h"
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#endif /* !_ASMLANGUAGE */
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#endif /* _SOC__H_ */

‎soc/silabs/silabs_s0/efm32tg/soc_pinmap.h

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/*
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* Copyright (c) 2025 Lukas Woodtli
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Silabs EFM32TG MCU pin definitions.
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*
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* This file contains pin configuration data required by different MCU
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* modules to correctly configure GPIO controller.
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*/
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#ifndef _SILABS_EFM32TG_SOC_PINMAP_H_
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#define _SILABS_EFM32TG_SOC_PINMAP_H_
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#include <soc.h>
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#include <em_gpio.h>
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#endif /* _SILABS_EFM32TG_SOC_PINMAP_H_ */

‎soc/silabs/soc.yml

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- name: efm32hg
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socs:
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- name: efm32hg322f64
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- name: efm32tg
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socs:
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- name: efm32tg840f32
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- name: silabs_s1
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series:
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- name: efm32pg1b

‎west.yml

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groups:
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- hal
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- name: hal_silabs
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revision: 389726f350880238b9a1034f575ffd46c4309827
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revision: f16db77700c38c0f69b5324f3d75945541f52f37
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path: modules/hal/silabs
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groups:
241241
- hal

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