arch: riscv: streamline fatal handling code

`CONFIG_EXTRA_EXCEPTION_INFO` that was added in #78065 doesn't
seem necessary, as we were already storing and printing the
callee-saved-registers before that. All `CONFIG_EXTRA_EXCEPTION_INFO`
does in RISCV is to add an additional `_callee_saved_t *csf` in the
`struct arch_esf`, which overhead is negligible to what's being enabled
by `CONFIG_EXCEPTION_DEBUG`.

Let's remove `CONFIG_EXTRA_EXCEPTION_INFO`, and have that extra
`_callee_saved_t *csf` in the `struct arch_esf` as long as
`CONFIG_EXCEPTION_DEBUG` is enabled.

Then, since `*csf` is always available in the `struct arch_esf` when
`CONFIG_EXCEPTION_DEBUG=y`, we can simply rely on that pointer in
`z_riscv_fatal_error()` instead of an additional argument in
`z_riscv_fatal_error_csf()`, rendering it redundant and thus can be
removed.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>

Author: ycsin

arch/riscv/Kconfig

@@ -301,14 +301,6 @@ config RISCV_HART_MASK
 	  i.e. 128, 129, ..(0x80, 8x81, ..), this can be configured to 63 (0x7f)
 	  such that we can extract the bits that start from 0.
 
-config EXTRA_EXCEPTION_INFO
-	bool "Collect extra exception info"
-	depends on EXCEPTION_DEBUG
-	help
-	  This option enables the collection of extra information, such as
-	  register state, when a fault occurs. This information can be useful
-	  to collect for post-mortem analysis and debug of issues.
-
 config RISCV_PMP
 	bool "RISC-V PMP Support"
 	select THREAD_STACK_INFO

arch/riscv/core/fatal.c

@@ -80,12 +80,7 @@ const char *z_riscv_mcause_str(unsigned long cause)
 FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
 				       const struct arch_esf *esf)
 {
-	z_riscv_fatal_error_csf(reason, esf, NULL);
-}
-
-FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arch_esf *esf,
-					   const _callee_saved_t *csf)
-{
+	__maybe_unused _callee_saved_t *csf = NULL;
 	unsigned long mcause;
 
 	__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
@@ -122,6 +117,8 @@ FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arc
 		LOG_ERR("   mepc: " PR_REG, esf->mepc);
 		LOG_ERR("mstatus: " PR_REG, esf->mstatus);
 		LOG_ERR("");
+
+		csf = esf->csf;
 	}
 
 	if (csf != NULL) {
@@ -248,6 +245,12 @@ void z_impl_user_fault(unsigned int reason)
 {
 	struct arch_esf *oops_esf = _current->syscall_frame;
 
+#ifdef CONFIG_EXCEPTION_DEBUG
+	if (oops_esf != NULL) {
+		oops_esf->csf = NULL;
+	}
+#endif /* CONFIG_EXCEPTION_DEBUG */
+
 	if (((_current->base.user_options & K_USER) != 0) &&
 		reason != K_ERR_STACK_CHK_FAIL) {
 		reason = K_ERR_KERNEL_OOPS;

arch/riscv/core/isr.S

@@ -78,12 +78,7 @@ GTEXT(__soc_save_context)
 GTEXT(__soc_restore_context)
 #endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
 
-#ifdef CONFIG_EXCEPTION_DEBUG
-GTEXT(z_riscv_fatal_error_csf)
-#else
 GTEXT(z_riscv_fatal_error)
-#endif /* CONFIG_EXCEPTION_DEBUG */
-
 GTEXT(z_get_next_switch_handle)
 GTEXT(z_riscv_switch)
 GTEXT(z_riscv_thread_start)
@@ -468,19 +463,13 @@ do_fault:
 	/* Allocate space for caller-saved registers on current thread stack */
 	addi sp, sp, -__callee_saved_t_SIZEOF
 
-	/* Save callee-saved registers to be passed as 3rd arg */
+	/* Save callee-saved registers */
 	STORE_CALLEE_SAVED()		;
-	mv a2, sp
 
-#ifdef CONFIG_EXTRA_EXCEPTION_INFO
 	/* Store csf's addr into esf (a1 still holds the pointer to the esf at this point) */
-	sr a2 __struct_arch_esf_csf_OFFSET(a1)
-#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
-
-	tail z_riscv_fatal_error_csf
-#else
-	tail z_riscv_fatal_error
+	sr sp __struct_arch_esf_csf_OFFSET(a1)
 #endif /* CONFIG_EXCEPTION_DEBUG */
+	tail z_riscv_fatal_error
 
 #if defined(CONFIG_IRQ_OFFLOAD)
 do_irq_offload:

arch/riscv/core/offsets/offsets.c

@@ -122,10 +122,6 @@ GEN_OFFSET_STRUCT(arch_esf, s0);
 GEN_OFFSET_STRUCT(arch_esf, sp);
 #endif
 
-#ifdef CONFIG_EXTRA_EXCEPTION_INFO
-GEN_OFFSET_STRUCT(arch_esf, csf);
-#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
-
 #if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE)
 GEN_OFFSET_STRUCT(arch_esf, soc_context);
 #endif
@@ -136,6 +132,7 @@ GEN_SOC_OFFSET_SYMS();
 GEN_ABSOLUTE_SYM(__struct_arch_esf_SIZEOF, sizeof(struct arch_esf));
 
 #ifdef CONFIG_EXCEPTION_DEBUG
+GEN_OFFSET_STRUCT(arch_esf, csf);
 GEN_ABSOLUTE_SYM(__callee_saved_t_SIZEOF, ROUND_UP(sizeof(_callee_saved_t), ARCH_STACK_PTR_ALIGN));
 #endif /* CONFIG_EXCEPTION_DEBUG */
 

arch/riscv/include/kernel_arch_func.h

@@ -74,13 +74,9 @@ arch_switch(void *switch_to, void **switched_from)
 #endif
 }
 
-/* Thin wrapper around z_riscv_fatal_error_csf */
 FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
 				       const struct arch_esf *esf);
 
-FUNC_NORETURN void z_riscv_fatal_error_csf(unsigned int reason, const struct arch_esf *esf,
-					   const _callee_saved_t *csf);
-
 static inline bool arch_is_in_isr(void)
 {
 #ifdef CONFIG_SMP

doc/releases/migration-guide-4.2.rst

@@ -760,3 +760,9 @@ Architectures
   of vector table in RAM.
 * Renamed :kconfig:option:`CONFIG_DEBUG_INFO` to :kconfig:option:`CONFIG_X86_DEBUG_INFO` to
   better reflect its purpose. This option is now only available for x86 architecture.
+
+* RISCV
+
+  * :kconfig:option:`CONFIG_EXTRA_EXCEPTION_INFO` has been removed, the ``*csf`` pointer will be
+    available in the ``struct arch_esf`` when :kconfig:option:`CONFIG_EXCEPTION_DEBUG` is
+    enabled.

include/zephyr/arch/riscv/exception.h

@@ -45,11 +45,11 @@ struct soc_esf {
 };
 #endif
 
-#ifdef CONFIG_EXTRA_EXCEPTION_INFO
+#ifdef CONFIG_EXCEPTION_DEBUG
 /* Forward declaration */
 struct _callee_saved;
 typedef struct _callee_saved _callee_saved_t;
-#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
+#endif /* CONFIG_EXCEPTION_DEBUG */
 
 #if defined(CONFIG_RISCV_SOC_HAS_ISR_STACKING)
 	SOC_ISR_STACKING_ESF_DECLARE;
@@ -91,9 +91,9 @@ struct arch_esf {
 	unsigned long sp;		/* preserved (user or kernel) stack pointer */
 #endif
 
-#ifdef CONFIG_EXTRA_EXCEPTION_INFO
+#ifdef CONFIG_EXCEPTION_DEBUG
 	_callee_saved_t *csf;		/* pointer to callee-saved-registers */
-#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
+#endif /* CONFIG_EXCEPTION_DEBUG */
 
 #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
 	struct soc_esf soc_context;

soc/nordic/common/vpr/soc_isr_stacking.h

@@ -14,13 +14,20 @@
 
 #define VPR_CPU DT_INST(0, nordic_vpr)
 
+#ifdef CONFIG_EXCEPTION_DEBUG
+#define ESF_CSF _callee_saved_t *csf
+#else
+#define ESF_CSF
+#endif /* CONFIG_EXCEPTION_DEBUG */
+
 #if DT_PROP(VPR_CPU, nordic_bus_width) == 64
 
 #define SOC_ISR_STACKING_ESF_DECLARE                                                               \
 	struct arch_esf {                                                                          \
 		unsigned long s0;                                                                  \
 		unsigned long mstatus;                                                             \
 		struct soc_esf soc_context;                                                        \
+		ESF_CSF;                                                                           \
                                                                                                    \
 		unsigned long t2;                                                                  \
 		unsigned long ra;                                                                  \
@@ -43,6 +50,7 @@
 		unsigned long s0;                                                                  \
 		unsigned long mstatus;                                                             \
 		struct soc_esf soc_context;                                                        \
+		ESF_CSF;                                                                           \
                                                                                                    \
 		unsigned long ra;                                                                  \
 		unsigned long t2;                                                                  \