@@ -35,25 +35,25 @@ LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
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#define out_w1ts out_w1ts.val
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#define out_w1tc out_w1tc.val
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/* arch_curr_cpu() is not available for riscv based chips */
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- #define CPU_ID () 0
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+ #define ESP32_CPU_ID () 0
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#elif CONFIG_SOC_SERIES_ESP32C3
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/* gpio structs in esp32c3 series are different from xtensa ones */
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#define out out.data
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#define in in.data
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#define out_w1ts out_w1ts.val
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#define out_w1tc out_w1tc.val
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/* arch_curr_cpu() is not available for riscv based chips */
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- #define CPU_ID () 0
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+ #define ESP32_CPU_ID () 0
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#elif defined(CONFIG_SOC_SERIES_ESP32C6 )
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/* gpio structs in esp32c6 are also different */
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#define out out.out_data_orig
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#define in in.in_data_next
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#define out_w1ts out_w1ts.val
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#define out_w1tc out_w1tc.val
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/* arch_curr_cpu() is not available for riscv based chips */
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- #define CPU_ID () 0
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+ #define ESP32_CPU_ID () 0
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#else
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- #define CPU_ID () arch_curr_cpu()->id
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+ #define ESP32_CPU_ID () arch_curr_cpu()->id
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#endif
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#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
@@ -413,7 +413,7 @@ static int gpio_esp32_pin_interrupt_configure(const struct device *port,
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}
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gpio_ll_set_intr_type (cfg -> gpio_base , io_pin , intr_trig_mode );
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- gpio_ll_intr_enable_on_core (cfg -> gpio_base , CPU_ID (), io_pin );
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+ gpio_ll_intr_enable_on_core (cfg -> gpio_base , ESP32_CPU_ID (), io_pin );
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irq_unlock (key );
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return 0 ;
@@ -432,7 +432,7 @@ static uint32_t gpio_esp32_get_pending_int(const struct device *dev)
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{
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const struct gpio_esp32_config * const cfg = dev -> config ;
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uint32_t irq_status ;
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- uint32_t const core_id = CPU_ID ();
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+ uint32_t const core_id = ESP32_CPU_ID ();
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if (cfg -> gpio_port == 0 ) {
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gpio_ll_get_intr_status (cfg -> gpio_base , core_id , & irq_status );
@@ -448,7 +448,7 @@ static void IRAM_ATTR gpio_esp32_fire_callbacks(const struct device *dev)
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const struct gpio_esp32_config * const cfg = dev -> config ;
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struct gpio_esp32_data * data = dev -> data ;
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uint32_t irq_status ;
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- uint32_t const core_id = CPU_ID ();
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+ uint32_t const core_id = ESP32_CPU_ID ();
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if (cfg -> gpio_port == 0 ) {
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gpio_ll_get_intr_status (cfg -> gpio_base , core_id , & irq_status );
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