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KATE-WANG-NXPkartben
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drivers: video: ov7670: update the camera init sequence
The previous initialization sequence fails to configure the module properly. Update the sequence using the code provided by vendor. The update is verified using the FRDM-MCXN947 SmartDMA camera case under samples/drivers/video/capture. Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
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drivers/video/ov7670.c

Lines changed: 23 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -219,21 +219,37 @@ static const struct ov7670_reg ov7670_init_regtbl[] = {
219219
{OV7670_MVFP, 0x00}, /* MVFP: Mirror/VFlip,Normal image */
220220

221221
/* configure the output timing */
222-
/* Free running PCLK, default VSYNC, HSYNC and PCLK */
223-
{OV7670_COM10, 0x00}, /* COM10 */
222+
/* PCLK does not toggle during horizontal blank, one PCLK, one pixel */
223+
{OV7670_COM10, 0x20}, /* COM10 */
224224
{OV7670_COM12, 0x00}, /* COM12,No HREF when VSYNC is low */
225225
/* Brightness Control, with signal -128 to +128, 0x00 is middle value */
226226
{OV7670_BRIGHT, 0x2f},
227227

228228
/* Internal clock pre-scalar,F(internal clock) = F(input clock)/(Bit[5:0]+1) */
229-
{OV7670_CLKRC, 0x80}, /* Clock Div, Input/(n+1), bit6 set to 1 to disable divider */
229+
{OV7670_CLKRC, 0x81}, /* Clock Div, Input/(n+1), bit6 set to 1 to disable divider */
230+
231+
/* SCALING_PCLK_DIV */
232+
/* 0: Enable clock divider, 010: Divided by 4 */
233+
{OV7670_SCALING_PCLK_DIV, 0xF1},
234+
/* Common Control 14, Bit[4]: DCW and scaling PCLK enable, Bit[3]: Manual scaling */
235+
{OV7670_COM14, 0x19},
236+
/* Common Control 3, Bit[2]: DCW enable, Bit[3]: Scale enable */
237+
{OV7670_COM3, 0x04},
230238

231239
/* DBLV,Bit[7:6]: PLL control */
232240
/* 0:Bypass PLL, 40: Input clock x4 , 80: Input clock x6 ,C0: Input clock x8 */
233-
{OV7670_DBLV, 0x00},
241+
{OV7670_DBLV, 0x40},
242+
243+
/* test pattern, useful in some case */
244+
{OV7670_SCALING_XSC, 0x3A},
245+
{OV7670_SCALING_YSC, 0x35},
246+
247+
/* DCW Control */
248+
{OV7670_SCALING_DCWCTR, 0x11},
234249

235250
/* Output Drive Capability */
236251
{OV7670_COM2, 0x00}, /* Common Control 2, Output Drive Capability: 1x */
252+
{OV7670_SCALING_PCLK_DELAY, 0x02},
237253
{OV7670_BD50MAX, 0x05},
238254
{OV7670_BD60MAX, 0x07},
239255
{OV7670_HAECC7, 0x94},
@@ -265,13 +281,13 @@ static const struct ov7670_reg ov7670_init_regtbl[] = {
265281

266282
/* display , need retain */
267283
{OV7670_COM15, 0xD0}, /* Common Control 15 */
268-
{OV7670_TSLB, 0x04}, /* Reserved */
284+
{OV7670_TSLB, 0x0C}, /* Line Buffer Test Option */
269285
{OV7670_COM13, 0x80}, /* Common Control 13 */
270286
{OV7670_MANU, 0x11}, /* Manual U Value */
271287
{OV7670_MANV, 0xFF}, /* Manual V Value */
272288
/* config the output window data, this can be configed later */
273-
{OV7670_HSTART, 0x16}, /* HSTART */
274-
{OV7670_HSTOP, 0x04}, /* HSTOP */
289+
{OV7670_HSTART, 0x15}, /* HSTART */
290+
{OV7670_HSTOP, 0x03}, /* HSTOP */
275291
{OV7670_VSTRT, 0x02}, /* VSTRT */
276292
{OV7670_VSTOP, 0x7a}, /* VSTOP */
277293
{OV7670_HREF, 0x80}, /* HREF */

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