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Zhiqiang-Houkartben
Zhiqiang-Hou
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kartben
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soc: nxp: add SoC imx91 support
The i.MX 91 SoC’s integrated EdgeLock® Secure Enclave provides security features including lifecycle management, tamper detection, secure boot and a simplified path to certifications. The i.MX 91 family features an Arm® Cortex®-A55 running at up to 1.4GHz, support for modern LPDDR4 memory to enable platform longevity, dual Gigabit Ethernet and dual USB ports, along with a rich set of peripherals targeting medical, industrial and consumer IoT market segments. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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‎soc/nxp/imx/imx9/CMakeLists.txt

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# Copyright 2024 NXP
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# Copyright 2024-2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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if(CONFIG_SOC_MIMX9352)
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if(CONFIG_SOC_MIMX9131)
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add_subdirectory(imx91)
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elseif(CONFIG_SOC_MIMX9352)
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add_subdirectory(imx93)
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elseif(CONFIG_SOC_MIMX9596)
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add_subdirectory(imx95)

‎soc/nxp/imx/imx9/imx91/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_compile_options(-Wno-misleading-indentation)
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zephyr_include_directories(.)
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zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

‎soc/nxp/imx/imx9/imx91/Kconfig

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_MIMX9131
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select ARM64
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select CPU_CORTEX_A55
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select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
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select HAS_MCUX if CLOCK_CONTROL
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select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL
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select HAS_MCUX_IOMUXC if PINCTRL
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select HAS_MCUX_CACHE
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select KERNEL_DIRECT_MAP if HAS_MCUX

‎soc/nxp/imx/imx9/imx91/Kconfig.defconfig

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_IMX9
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rsource "Kconfig.defconfig.*"
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endif # SOC_SERIES_IMX9

‎soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MIMX9131
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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config NUM_IRQS
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default 300
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 24000000
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endif

‎soc/nxp/imx/imx9/imx91/Kconfig.soc

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_MIMX9131
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bool
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select SOC_SERIES_IMX9
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help
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NXP i.MX91
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config SOC_PART_NUMBER_MIMX9131CVVXJ
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bool
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config SOC_PART_NUMBER_MIMX9131DVVXJ
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bool
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config SOC_PART_NUMBER
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default "MIMX9131CVVXJ" if SOC_PART_NUMBER_MIMX9131CVVXJ
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default "MIMX9131DVVXJ" if SOC_PART_NUMBER_MIMX9131DVVXJ
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config SOC
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default "mimx9131" if SOC_MIMX9131

‎soc/nxp/imx/imx9/imx91/mmu_regions.c

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm64/arm_mmu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
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DT_REG_SIZE(DT_NODELABEL(ana_pll)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
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DT_REG_SIZE(DT_NODELABEL(iomuxc)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_lpuart,
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(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};

‎soc/nxp/imx/imx9/imx91/pinctrl_soc.h

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#include "fsl_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT
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#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT
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#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT
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#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT
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#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT
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#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT
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#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
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#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
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#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \
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((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
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(DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
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(DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \
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(DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \
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(DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \
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((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \
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(DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
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/* This struct must be present. It is used by the mcux gpio driver */
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struct pinctrl_soc_pinmux {
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uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */
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uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
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uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */
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uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */
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uint32_t input_daisy: 4; /*!< Mux value for SELECT_INPUT_DAISY register */
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};
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struct pinctrl_soc_pin {
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struct pinctrl_soc_pinmux pinmux;
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uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
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};
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typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
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/* This definition must be present. It is used by the mcux gpio driver */
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#define MCUX_IMX_PINMUX(node_id) \
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{ \
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.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \
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.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \
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.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \
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.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \
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.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \
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}
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#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \
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MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
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#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \
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{ \
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.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \
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.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \
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},
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ */

‎soc/nxp/imx/soc.yml

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- name: m4
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- name: imx9
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socs:
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- name: mimx9131
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- name: mimx9352
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cpuclusters:
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- name: a55

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