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frank-kuedanieldegrasse
frank-kue
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danieldegrasse
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drivers: reset: Add MPFS MSS driver
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft reset control. Normally, the peripheral clocks and reset state are controlled by the Hart Software Services (HSS) running on the Monitor processor. As an alternative to using HSS services, applications can now enable the reset controller in a device tree overly, for example: &reset { status = "okay"; }; &uart4 { resets = <&reset MSS_RESET_ID_MMUART4>; }; Embedded the reset controller node in system controller node. Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
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‎drivers/reset/CMakeLists.txt

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@@ -13,3 +13,4 @@ zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NXP_SYSCON reset_lpc_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_MMIO reset_mmio.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_MCHP_MSS reset_mchp_mss.c)

‎drivers/reset/Kconfig

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@@ -37,5 +37,6 @@ rsource "Kconfig.npcx"
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rsource "Kconfig.lpc_syscon"
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rsource "Kconfig.nxp_rstctl"
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rsource "Kconfig.mmio"
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rsource "Kconfig.mchp_mss"
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endif # RESET

‎drivers/reset/Kconfig.mchp_mss

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# Copyright (c) 2025 Microchip Technology Inc
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# SPDX-License-Identifier: Apache-2.0
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config RESET_MCHP_MSS
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bool "Microchip PolarFire SoC and PIC64GX reset driver"
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depends on DT_HAS_MICROCHIP_MPFS_RESET_ENABLED
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help
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This option enables the reset driver for Microchip's PolarFire SoC
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and PIC64GX platform.

‎drivers/reset/reset_mchp_mss.c

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/*
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* Copyright (C) 2025 embedded brains GmbH & Co. KG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_mpfs_reset
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/reset.h>
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#define SUBBLK_CLOCK_CR_OFFSET 0x84U
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#define SOFT_RESET_CR_OFFSET 0x88U
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#define RESET_MSS_REG_BIT(id) ((id) & 0x1fU)
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/* Bit 17 is related to the FPGA, bits 30 and 31 are reserved */
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#define RESET_MSS_VALID_BITS 0x3ffdffffU
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struct reset_mss_config {
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uintptr_t base;
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};
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static int reset_mss_status(const struct device *dev, uint32_t id, uint8_t *status)
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{
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const struct reset_mss_config *config = dev->config;
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/* Device is in reset if the clock is turned off or held in soft reset */
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*status = sys_test_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, RESET_MSS_REG_BIT(id)) == 0 ||
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sys_test_bit(config->base + SOFT_RESET_CR_OFFSET, RESET_MSS_REG_BIT(id) != 0);
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return 0;
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}
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static int reset_mss_line_assert(const struct device *dev, uint32_t id)
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{
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const struct reset_mss_config *config = dev->config;
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unsigned int bit = RESET_MSS_REG_BIT(id);
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if (!IS_BIT_SET(RESET_MSS_VALID_BITS, bit)) {
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return -EINVAL;
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}
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/* Turn off clock */
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sys_clear_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, bit);
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/* Hold in reset */
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sys_set_bit(config->base + SOFT_RESET_CR_OFFSET, bit);
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return 0;
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}
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static int reset_mss_line_deassert(const struct device *dev, uint32_t id)
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{
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const struct reset_mss_config *config = dev->config;
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unsigned int bit = RESET_MSS_REG_BIT(id);
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if (!IS_BIT_SET(RESET_MSS_VALID_BITS, bit)) {
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return -EINVAL;
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}
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/* Turn on clock */
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sys_set_bit(config->base + SUBBLK_CLOCK_CR_OFFSET, bit);
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/* Remove soft reset */
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sys_clear_bit(config->base + SOFT_RESET_CR_OFFSET, bit);
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return 0;
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}
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static int reset_mss_line_toggle(const struct device *dev, uint32_t id)
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{
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reset_mss_line_assert(dev, id);
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reset_mss_line_deassert(dev, id);
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return 0;
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}
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static DEVICE_API(reset, reset_mss_driver_api) = {
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.status = reset_mss_status,
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.line_assert = reset_mss_line_assert,
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.line_deassert = reset_mss_line_deassert,
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.line_toggle = reset_mss_line_toggle
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};
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static const struct reset_mss_config reset_mss_config = {
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.base = DT_REG_ADDR(DT_INST_PARENT(0))
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_mss_config, PRE_KERNEL_1,
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CONFIG_RESET_INIT_PRIORITY, &reset_mss_driver_api);

‎dts/bindings/reset/microchip,mpfs-reset.yaml

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#
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# Copyright (C) 2025 embedded brains GmbH & Co. KG
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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description: Microchip MPFS Reset Controller (SOFT_RESET_CR, SUBBLK_CLOCK_CR)
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compatible: "microchip,mpfs-reset"
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include: [base.yaml, reset-controller.yaml]
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properties:
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"#reset-cells":
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const: 1
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reset-cells:
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- id

‎dts/riscv/microchip/mpfs.dtsi

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#include <skeleton.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/reset/mchp_mss_reset.h>
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/ {
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#address-cells = <1>;
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status = "disabled";
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};
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mpfs_top_sysreg: syscon@20002000 {
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compatible = "syscon";
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reg = <0x20002000 0x1000>;
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reset: reset {
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compatible = "microchip,mpfs-reset";
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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uart0: uart@20000000 {
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compatible = "ns16550";
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reg = <0x20000000 0x1000>;

‎include/zephyr/dt-bindings/reset/mchp_mss_reset.h

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/*
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* Copyright (C) 2025 embedded brains GmbH & Co. KG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_
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/*
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* The reset ID encodes the bit index of the SUBBLK_CLOCK_CR and SOFT_RESET_CR
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* registers associated with the device.
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*/
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#define MSS_RESET_ID_ENVM 0x0
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#define MSS_RESET_ID_MAC0 0x1
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#define MSS_RESET_ID_MAC1 0x2
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#define MSS_RESET_ID_MMC 0x3
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#define MSS_RESET_ID_TIMER 0x4
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#define MSS_RESET_ID_MMUART0 0x5
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#define MSS_RESET_ID_MMUART1 0x6
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#define MSS_RESET_ID_MMUART2 0x7
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#define MSS_RESET_ID_MMUART3 0x8
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#define MSS_RESET_ID_MMUART4 0x9
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#define MSS_RESET_ID_SPI0 0xa
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#define MSS_RESET_ID_SPI1 0xb
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#define MSS_RESET_ID_I2C0 0xc
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#define MSS_RESET_ID_I2C1 0xd
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#define MSS_RESET_ID_CAN0 0xe
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#define MSS_RESET_ID_CAN1 0xf
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#define MSS_RESET_ID_USB 0x10
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#define MSS_RESET_ID_RSVD 0x11
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#define MSS_RESET_ID_RTC 0x12
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#define MSS_RESET_ID_QSPI 0x13
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#define MSS_RESET_ID_GPIO0 0x14
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#define MSS_RESET_ID_GPIO1 0x15
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#define MSS_RESET_ID_GPIO2 0x16
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#define MSS_RESET_ID_DDRC 0x17
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#define MSS_RESET_ID_FIC0 0x18
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#define MSS_RESET_ID_FIC1 0x19
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#define MSS_RESET_ID_FIC2 0x1a
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#define MSS_RESET_ID_FIC3 0x1b
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#define MSS_RESET_ID_ATHENA 0x1c
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#define MSS_RESET_ID_CFM 0x1d
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_ */

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