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FRASTMdanieldegrasse
FRASTM
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danieldegrasse
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dts: arm: stm32 reg definition for the st,stm32-ospi compatible
The st,stm32-ospi compatible is defining the reg property with the register address and size at first index followed by the external mem base address and max allocated size. For the stm32H7, stm32L4plus, stm32L5, stm32U5 series. ospi1 is addressing max 256 MBytes from 0x90000000 ospi2 is addressing max 256 MBytes from 0x70000000 Signed-off-by: Francois Ramu <francois.ramu@st.com>
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6 files changed

+31
-18
lines changed

6 files changed

+31
-18
lines changed

‎dts/arm/st/h7/stm32h723.dtsi

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -95,25 +95,25 @@
9595

9696
octospi1: spi@52005000 {
9797
compatible = "st,stm32-ospi";
98-
reg = <0x52005000 0x1000>;
98+
reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
9999
interrupts = <92 0>;
100100
clock-names = "ospix", "ospi-ker";
101101
clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
102102
<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
103103
#address-cells = <1>;
104-
#size-cells = <1>;
104+
#size-cells = <0>;
105105
status = "disabled";
106106
};
107107

108108
octospi2: spi@5200a000 {
109109
compatible = "st,stm32-ospi";
110-
reg = <0x5200a000 0x1000>;
110+
reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>;
111111
interrupts = <150 0>;
112112
clock-names = "ospix", "ospi-ker";
113113
clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
114114
<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
115115
#address-cells = <1>;
116-
#size-cells = <1>;
116+
#size-cells = <0>;
117117
status = "disabled";
118118
};
119119

‎dts/arm/st/h7/stm32h7a3.dtsi

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,25 +58,25 @@
5858

5959
octospi1: spi@52005000 {
6060
compatible = "st,stm32-ospi";
61-
reg = <0x52005000 0x1000>;
61+
reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
6262
interrupts = <92 0>;
6363
clock-names = "ospix", "ospi-ker";
6464
clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
6565
<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
6666
#address-cells = <1>;
67-
#size-cells = <1>;
67+
#size-cells = <0>;
6868
status = "disabled";
6969
};
7070

7171
octospi2: spi@5200a000 {
7272
compatible = "st,stm32-ospi";
73-
reg = <0x5200a000 0x1000>;
73+
reg = <0x5200a000 0x1000>, <0x70000000 DT_SIZE_M(256)>;
7474
interrupts = <150 0>;
7575
clock-names = "ospix", "ospi-ker";
7676
clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
7777
<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
7878
#address-cells = <1>;
79-
#size-cells = <1>;
79+
#size-cells = <0>;
8080
status = "disabled";
8181
};
8282

‎dts/arm/st/l4/stm32l4p5.dtsi

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -379,29 +379,29 @@
379379

380380
octospi1: spi@a0001000 {
381381
compatible = "st,stm32-ospi";
382-
reg = <0xa0001000 0x400>;
382+
reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>;
383383
interrupts = <71 0>;
384384
clock-names = "ospix", "ospi-ker", "ospi-mgr";
385385
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
386386
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
387387
<&rcc STM32_CLOCK(AHB2, 20U)>;
388388

389389
#address-cells = <1>;
390-
#size-cells = <1>;
390+
#size-cells = <0>;
391391
status = "disabled";
392392
};
393393

394394
octospi2: spi@a0001400 {
395395
compatible = "st,stm32-ospi";
396-
reg = <0xa0001400 0x400>;
396+
reg = <0xa0001400 0x400>, <0x70000000 DT_SIZE_M(256)>;
397397
interrupts = <76 0>;
398398
clock-names = "ospix", "ospi-ker", "ospi-mgr";
399399
clocks = <&rcc STM32_CLOCK(AHB3, 9U)>,
400400
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
401401
<&rcc STM32_CLOCK(AHB2, 20U)>;
402402

403403
#address-cells = <1>;
404-
#size-cells = <1>;
404+
#size-cells = <0>;
405405
status = "disabled";
406406
};
407407
};

‎dts/arm/st/l5/stm32l5.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -434,13 +434,13 @@
434434

435435
octospi1: spi@44021000 {
436436
compatible = "st,stm32-ospi";
437-
reg = <0x44021000 0x400>;
437+
reg = <0x44021000 0x400>, <0x90000000 DT_SIZE_M(256)>;
438438
interrupts = <76 0>;
439439
clock-names = "ospix", "ospi-ker";
440440
clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
441441
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>;
442442
#address-cells = <1>;
443-
#size-cells = <1>;
443+
#size-cells = <0>;
444444
status = "disabled";
445445
};
446446

‎dts/arm/st/u5/stm32u5.dtsi

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -695,14 +695,27 @@
695695

696696
octospi1: spi@420d1400 {
697697
compatible = "st,stm32-ospi";
698-
reg = <0x420d1400 0x400>;
698+
reg = <0x420d1400 0x400>, <0x90000000 DT_SIZE_M(256)>;
699699
interrupts = <76 0>;
700700
clock-names = "ospix", "ospi-ker", "ospi-mgr";
701701
clocks = <&rcc STM32_CLOCK(AHB2_2, 4)>,
702702
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
703703
<&rcc STM32_CLOCK(AHB2, 21)>;
704704
#address-cells = <1>;
705-
#size-cells = <1>;
705+
#size-cells = <0>;
706+
status = "disabled";
707+
};
708+
709+
octospi2: spi@420d2400 {
710+
compatible = "st,stm32-ospi";
711+
reg = <0x420d2400 0x400>, <0x70000000 DT_SIZE_M(256)>;
712+
interrupts = <120 0>;
713+
clock-names = "ospix", "ospi-ker", "ospi-mgr";
714+
clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>,
715+
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
716+
<&rcc STM32_CLOCK(AHB2, 21U)>;
717+
#address-cells = <1>;
718+
#size-cells = <0>;
706719
status = "disabled";
707720
};
708721

‎dts/arm/st/u5/stm32u5_extra.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,14 +57,14 @@
5757

5858
octospi2: spi@420d2400 {
5959
compatible = "st,stm32-ospi";
60-
reg = <0x420d2400 0x400>;
60+
reg = <0x420d2400 0x400>, <0x70000000 DT_SIZE_M(256)>;
6161
interrupts = <120 0>;
6262
clock-names = "ospix", "ospi-ker", "ospi-mgr";
6363
clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>,
6464
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
6565
<&rcc STM32_CLOCK(AHB2, 21)>;
6666
#address-cells = <1>;
67-
#size-cells = <1>;
67+
#size-cells = <0>;
6868
status = "disabled";
6969
};
7070

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