boards: imx8mp_evk: a53: enable FlexCAN on the board

JiafeiPan · kartben · commit d5b9e744762f · 2025-06-25T09:52:56.000+02:00
Added dts nodes of FlexCAN1 and FlexCAN2 in SoC dts.
Added dts nodes and overlay in imx8mp_evk board.

Signed-off-by: Jiafei Pan &lt;Jiafei.Pan@nxp.com&gt;
diff --git a/boards/nxp/imx8mp_evk/Kconfig.defconfig b/boards/nxp/imx8mp_evk/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_IMX8MP_EVK
@@ -39,6 +39,15 @@ endif # NET_SOCKETS_SERVICE
 
 endif # NETWORKING
 
+if CAN && GPIO_PCA6416
+
+# For FlexCAN2, SAI5 PDM/CAN2 IOMUX select is controlled by IO expandor PCA6416
+# IO port, so CAN transceiver must be initialized after PCA6416 initialization
+config CAN_TRANSCEIVER_INIT_PRIORITY
+	default 75
+
+endif # CAN && GPIO_PCA6416
+
 endif # BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP
 
 endif # BOARD_IMX8MP_EVK
diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst
@@ -180,6 +180,25 @@ display the following console output:
     thread_b: Hello World from cpu 0 on mimx8mp_evk!
     thread_a: Hello World from cpu 0 on mimx8mp_evk!
 
+CAN bus (FlexCAN) (A53)
+=======================
+The FlexCAN controller is a CAN 2.0B controller that supports both standard
+and extended frames. The FlexCAN controller has two independent FlexCAN
+modules, FlexCAN1 and FlexCAN2. By default, FlexCAN1 is enabled in the device
+tree. To enable FlexCAN2, you need to add the following overlay to the
+device tree:
+:zephyr_file:`boards/nxp/imx8mp_evk/dts/flexcan2.overlay`.
+
+For example, building the :zephyr:code-sample:`hello_world` sample with the CAN shell and
+CAN statistics enabled, and using the FlexCAN1 controller, you can use the following
+configuration:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: imx8mp_evk/mimx8ml8/a53
+   :gen-args: -DCONFIG_SHELL=y -DCONFIG_CAN=y -DCONFIG_CAN_SHELL=y -DCONFIG_STATS=y -DCONFIG_CAN_STATS=y
+   :goals: build
+
 Programming and Debugging (M7)
 ******************************
 
diff --git a/boards/nxp/imx8mp_evk/dts/flexcan2.overlay b/boards/nxp/imx8mp_evk/dts/flexcan2.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * DTS binding overlay for enabling FlexCAN2
+ */
+
+/ {
+	chosen {
+		zephyr,canbus = &flexcan2;
+	};
+};
+
+&can_phy2 {
+	status = "okay";
+};
+
+&flexcan2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi
@@ -7,6 +7,26 @@
 #include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
 
 &pinctrl {
+	flexcan1_default: flexcan1_default {
+		group0 {
+			pinmux = <&iomuxc_spdif_rx_can_rx_can1_rx>,
+				 <&iomuxc_spdif_tx_can_tx_can1_tx>;
+			bias-pull-up;
+			slew-rate = "fast";
+			drive-strength = "x2";
+		};
+	};
+
+	flexcan2_default: flexcan2_default {
+		group0 {
+			pinmux = <&iomuxc_sai5_mclk_can_rx_can2_rx>,
+				 <&iomuxc_sai5_rxd3_can_tx_can2_tx>;
+			bias-pull-up;
+			slew-rate = "fast";
+			drive-strength = "x2";
+		};
+	};
+
 	sai3_default: sai3_default {
 		group0 {
 			pinmux = <&iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync>,
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts
@@ -16,6 +16,7 @@
 	compatible = "fsl,mimx8mp";
 
 	chosen {
+		zephyr,canbus = &flexcan1;
 		zephyr,console = &uart4;
 		zephyr,shell-uart = &uart4;
 		/* sram node actually locates at DDR DRAM */
@@ -38,6 +39,23 @@
 		reg = <0xc0000000 DT_SIZE_M(1)>;
 	};
 
+	can_phy1: can-phy1{
+		compatible = "nxp,tja1048", "can-transceiver-gpio";
+		enable-gpios = <&gpio_exp1 2 GPIO_ACTIVE_LOW>;
+		standby-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+		max-bitrate = <8000000>;
+		#phy-cells = <0>;
+		status = "okay";
+	};
+
+	can_phy2: can-phy2{
+		compatible = "nxp,tja1048", "can-transceiver-gpio";
+		enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
+		standby-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+		max-bitrate = <8000000>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
 };
 
 &enet {
@@ -64,6 +82,20 @@
 	};
 };
 
+&flexcan1 {
+	pinctrl-0 = <&flexcan1_default>;
+	pinctrl-names = "default";
+	phys = <&can_phy1>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-0 = <&flexcan2_default>;
+	pinctrl-names = "default";
+	phys = <&can_phy2>;
+	status = "disabled";
+};
+
 &uart4 {
 	status = "okay";
 	current-speed = <115200>;
@@ -91,3 +123,7 @@
 &gpio1 {
 	status = "okay";
 };
+
+&gpio5 {
+	status = "okay";
+};
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml
@@ -13,10 +13,11 @@ toolchain:
   - cross-compile
 ram: 1024
 supported:
-  - uart
-  - net
+  - can
   - gpio
   - i2c
+  - net
+  - uart
 testing:
   ignore_tags:
     - bluetooth
diff --git a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2022,2024 NXP
+ * Copyright 2020-2022, 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -189,6 +189,34 @@
 			status = "disabled";
 		};
 
+		flexcan1: can@308c0000 {
+			compatible = "nxp,flexcan-fd", "nxp,flexcan";
+			reg = <0x308c0000 DT_SIZE_K(64)>;
+			interrupt-parent= <&gic>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+						<GIC_SPI 143 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "common", "error";
+			clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
+			clk-source = <0>;
+			rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\
+			       RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
+			status = "disabled";
+		};
+
+		flexcan2: can@308d0000 {
+			compatible = "nxp,flexcan-fd", "nxp,flexcan";
+			reg = <0x308d0000 DT_SIZE_K(64)>;
+			interrupt-parent= <&gic>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+						<GIC_SPI 145 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "common", "error";
+			clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 14>;
+			clk-source = <0>;
+			rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\
+			       RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>;
+			status = "disabled";
+		};
+
 		i2c1: i2c@30a20000 {
 			compatible = "nxp,ii2c";
 			#address-cells = <1>;
diff --git a/soc/nxp/imx/imx8m/a53/soc.c b/soc/nxp/imx/imx8m/a53/soc.c
@@ -51,6 +51,18 @@ static void soc_rdc_init(void)
 	periphConfig.policy = RDC_DT_VAL(i2c3);
 	RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
 #endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1)) && DT_NODE_HAS_PROP(DT_NODELABEL(flexcan1), rdc)
+	periphConfig.periph = kRDC_Periph_CAN_FD1;
+	periphConfig.policy = RDC_DT_VAL(flexcan1);
+	RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan2)) && DT_NODE_HAS_PROP(DT_NODELABEL(flexcan2), rdc)
+	periphConfig.periph = kRDC_Periph_CAN_FD2;
+	periphConfig.policy = RDC_DT_VAL(flexcan2);
+	RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
+#endif
 }
 #else
 
@@ -67,6 +79,18 @@ __weak void soc_clock_init(void)
 	CLOCK_SetRootDivider(kCLOCK_RootI2c3, 1U, 10U);
 	CLOCK_EnableClock(kCLOCK_I2c3);
 #endif
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1))
+	/* Set FLEXCAN1 source to SYSTEM PLL1 800MHZ */
+	CLOCK_SetRootMux(kCLOCK_RootFlexCan1, kCLOCK_FlexCanRootmuxSysPll1);
+	/* Set root clock to 800MHZ / 10 = 80MHZ */
+	CLOCK_SetRootDivider(kCLOCK_RootFlexCan1, 2U, 5U);
+#endif
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan2))
+	/* Set FLEXCAN2 source to SYSTEM PLL1 800MHZ */
+	CLOCK_SetRootMux(kCLOCK_RootFlexCan2, kCLOCK_FlexCanRootmuxSysPll1);
+	/* Set root clock to 800MHZ / 10 = 80MHZ */
+	CLOCK_SetRootDivider(kCLOCK_RootFlexCan2, 2U, 5U);
+#endif
 }
 
 void soc_prep_hook(void)
