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soc: atmel: sam4l: Enable RC32K osc
Enable sam4l internal factory calibrated RC32K clock source. The RC32K was used as source for Generic Clock 5 using 32 as divider. The output is a 1024 Hz clock that can be used by GLOC and TC0 peripherals. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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+91
-12
lines changed

2 files changed

+91
-12
lines changed

soc/atmel/sam/sam4l/soc.c

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,19 @@ static inline bool osc_is_ready(uint8_t id)
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}
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}
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59+
/**
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* Enable Backup System Control Oscilator RC32K
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*/
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static inline void osc_priv_enable_rc32k(void)
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{
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uint32_t temp = BSCIF->RC32KCR;
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uint32_t addr = (uint32_t)&BSCIF->RC32KCR - (uint32_t)BSCIF;
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BSCIF->UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)
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| BSCIF_UNLOCK_ADDR(addr);
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BSCIF->RC32KCR = temp | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN;
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}
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/**
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* The PLL options #PLL_OPT_VCO_RANGE_HIGH and #PLL_OPT_OUTPUT_DIV will
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* be set automatically based on the calculated target frequency.
@@ -153,6 +166,8 @@ static inline void flashcalw_issue_command(uint32_t command, int page_number)
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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uint32_t gen_clk_conf;
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/* Disable PicoCache and Enable HRAMC1 as extended RAM */
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soc_pmc_peripheral_enable(
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PM_CLOCK_MASK(PM_CLK_GRP_HSB, SYSCLK_HRAMC1_DATA));
@@ -224,6 +239,24 @@ static ALWAYS_INLINE void clock_init(void)
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PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
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PM_UNLOCK_ADDR((uint32_t)&PM->MCCTRL - (uint32_t)PM);
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PM->MCCTRL = OSC_SRC_PLL0;
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/** Enable RC32K Oscilator */
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osc_priv_enable_rc32k();
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while (!osc_is_ready(OSC_ID_RC32K)) {
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;
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}
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/** Enable Generic Clock 5
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* Source: RC32K
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* Div: 32
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* Clk: 1024 Hz
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* The GCLK-5 can be used by GLOC, TC0 and RC32KIFB_REF
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*/
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gen_clk_conf = SCIF_GCCTRL_RESETVALUE;
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gen_clk_conf |= SCIF_GCCTRL_OSCSEL(GEN_CLK_SRC_RC32K);
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gen_clk_conf |= SCIF_GCCTRL_DIVEN;
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gen_clk_conf |= SCIF_GCCTRL_DIV(((32 + 1) / 2) - 1);
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SCIF->GCCTRL[GEN_CLK_TC0_GLOC_RC32] = gen_clk_conf | SCIF_GCCTRL_CEN;
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}
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229262
void soc_reset_hook(void)

soc/atmel/sam/sam4l/soc.h

Lines changed: 58 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -208,18 +208,64 @@
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* 10- ADCIFE
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* 11- Master generic clock. Can be used as source for other generic clocks.
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*/
211-
#define GEN_CLK_DFLL_REF 0
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#define GEN_CLK_DFLL_DITHER 1
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#define GEN_CLK_AST 2
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#define GEN_CLK_CATB 3
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#define GEN_CLK_AESA 4
216-
#define GEN_CLK_GLOC 5
217-
#define GEN_CLK_ABDACB 6
218-
#define GEN_CLK_USBC 7
219-
#define GEN_CLK_TC1_PEVC0 8
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#define GEN_CLK_PLL0_PEVC1 9
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#define GEN_CLK_ADCIFE 10
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#define GEN_CLK_MASTER_GEN 11
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#define GEN_CLK_DFLL_REF 0
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#define GEN_CLK_DFLL_DITHER 1
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#define GEN_CLK_AST 2
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#define GEN_CLK_CATB 3
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#define GEN_CLK_AESA 4
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#define GEN_CLK_TC0_GLOC_RC32 5
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#define GEN_CLK_ABDACB 6
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#define GEN_CLK_USBC 7
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#define GEN_CLK_TC1_PEVC0 8
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#define GEN_CLK_PLL0_PEVC1 9
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#define GEN_CLK_ADCIFE 10
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#define GEN_CLK_MASTER_GEN 11
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/**
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* 0- System RC oscillator
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* 1- 32 kHz oscillator
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* 2- DFLL
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* 3- Oscillator 0
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* 4- 80 MHz RC oscillator
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* 5- 4-8-12 MHz RC oscillator
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* 6- 1 MHz RC oscillator
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* 7- CPU clock
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* 8- High Speed Bus clock
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* 9- Peripheral Bus A clock
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* 10- Peripheral Bus B clock
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* 11- Peripheral Bus C clock
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* 12- Peripheral Bus D clock
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* 13- 32 kHz RC oscillator
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* 15- 1 kHz output from OSC32K
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* 16- PLL0
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* 17- High resolution prescaler
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* 18- Fractional prescaler
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* 19- GCLKIN0
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* 20- GCLKIN1
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* 21- GCLK11
246+
*/
247+
248+
#define GEN_CLK_SRC_RCSYS 0
249+
#define GEN_CLK_SRC_OSC32K 1
250+
#define GEN_CLK_SRC_DFLL 2
251+
#define GEN_CLK_SRC_OSC0 3
252+
#define GEN_CLK_SRC_RC80M 4
253+
#define GEN_CLK_SRC_RCFAST 5
254+
#define GEN_CLK_SRC_RC1M 6
255+
#define GEN_CLK_SRC_CLK_CPU 7
256+
#define GEN_CLK_SRC_CLK_HSB 8
257+
#define GEN_CLK_SRC_CLK_PBA 9
258+
#define GEN_CLK_SRC_CLK_PBB 10
259+
#define GEN_CLK_SRC_CLK_PBC 11
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#define GEN_CLK_SRC_CLK_PBD 12
261+
#define GEN_CLK_SRC_RC32K 13
262+
#define GEN_CLK_SRC_CLK_1K 15
263+
#define GEN_CLK_SRC_PLL0 16
264+
#define GEN_CLK_SRC_HRPCLK 17
265+
#define GEN_CLK_SRC_FPCLK 18
266+
#define GEN_CLK_SRC_GCLKIN0 19
267+
#define GEN_CLK_SRC_GCLKIN1 20
268+
#define GEN_CLK_SRC_GCLK11 21
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#endif /* !_ASMLANGUAGE */
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