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18 | 18 |
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19 | 19 | LOG_MODULE_REGISTER(can_numaker, CONFIG_CAN_LOG_LEVEL);
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20 | 20 |
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21 |
| -/* CANFD Clock Source Selection */ |
22 |
| -#define NUMAKER_CANFD_CLKSEL_HXT 0 |
23 |
| -#define NUMAKER_CANFD_CLKSEL_PLL_DIV2 1 |
24 |
| -#define NUMAKER_CANFD_CLKSEL_HCLK 2 |
25 |
| -#define NUMAKER_CANFD_CLKSEL_HIRC 3 |
26 |
| - |
27 | 21 | /* Implementation notes
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28 | 22 | * 1. Use Bosch M_CAN driver (m_can) as backend
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29 | 23 | * 2. Need to modify can_numaker_get_core_clock() for new SOC support
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@@ -55,18 +49,33 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate)
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55 | 49 | clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1;
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56 | 50 |
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57 | 51 | switch (clksrc_rate_idx) {
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58 |
| - case NUMAKER_CANFD_CLKSEL_HXT: |
| 52 | +#if defined(CONFIG_SOC_SERIES_M46X) |
| 53 | + case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos): |
59 | 54 | *rate = __HXT / clkdiv_divider;
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60 | 55 | break;
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61 |
| - case NUMAKER_CANFD_CLKSEL_PLL_DIV2: |
| 56 | + case (CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 >> CLK_CLKSEL0_CANFD0SEL_Pos): |
62 | 57 | *rate = (CLK_GetPLLClockFreq() / 2) / clkdiv_divider;
|
63 | 58 | break;
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64 |
| - case NUMAKER_CANFD_CLKSEL_HCLK: |
| 59 | + case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos): |
65 | 60 | *rate = CLK_GetHCLKFreq() / clkdiv_divider;
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66 | 61 | break;
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67 |
| - case NUMAKER_CANFD_CLKSEL_HIRC: |
| 62 | + case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos): |
68 | 63 | *rate = __HIRC / clkdiv_divider;
|
69 | 64 | break;
|
| 65 | +#elif defined(CONFIG_SOC_SERIES_M2L31X) |
| 66 | + case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos): |
| 67 | + *rate = __HXT / clkdiv_divider; |
| 68 | + break; |
| 69 | + case (CLK_CLKSEL0_CANFD0SEL_HIRC48M >> CLK_CLKSEL0_CANFD0SEL_Pos): |
| 70 | + *rate = __HIRC48 / clkdiv_divider; |
| 71 | + break; |
| 72 | + case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos): |
| 73 | + *rate = CLK_GetHCLKFreq() / clkdiv_divider; |
| 74 | + break; |
| 75 | + case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos): |
| 76 | + *rate = __HIRC / clkdiv_divider; |
| 77 | + break; |
| 78 | +#endif |
70 | 79 | default:
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71 | 80 | LOG_ERR("Invalid clock source rate index");
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72 | 81 | return -EIO;
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