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ccli8kartben
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drivers: can: numaker: fix m2l31x core clock
This fixes canfd core clock for m2l31x soc. Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
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drivers/can/can_numaker.c

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,6 @@
1818

1919
LOG_MODULE_REGISTER(can_numaker, CONFIG_CAN_LOG_LEVEL);
2020

21-
/* CANFD Clock Source Selection */
22-
#define NUMAKER_CANFD_CLKSEL_HXT 0
23-
#define NUMAKER_CANFD_CLKSEL_PLL_DIV2 1
24-
#define NUMAKER_CANFD_CLKSEL_HCLK 2
25-
#define NUMAKER_CANFD_CLKSEL_HIRC 3
26-
2721
/* Implementation notes
2822
* 1. Use Bosch M_CAN driver (m_can) as backend
2923
* 2. Need to modify can_numaker_get_core_clock() for new SOC support
@@ -55,18 +49,33 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate)
5549
clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1;
5650

5751
switch (clksrc_rate_idx) {
58-
case NUMAKER_CANFD_CLKSEL_HXT:
52+
#if defined(CONFIG_SOC_SERIES_M46X)
53+
case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
5954
*rate = __HXT / clkdiv_divider;
6055
break;
61-
case NUMAKER_CANFD_CLKSEL_PLL_DIV2:
56+
case (CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 >> CLK_CLKSEL0_CANFD0SEL_Pos):
6257
*rate = (CLK_GetPLLClockFreq() / 2) / clkdiv_divider;
6358
break;
64-
case NUMAKER_CANFD_CLKSEL_HCLK:
59+
case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
6560
*rate = CLK_GetHCLKFreq() / clkdiv_divider;
6661
break;
67-
case NUMAKER_CANFD_CLKSEL_HIRC:
62+
case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
6863
*rate = __HIRC / clkdiv_divider;
6964
break;
65+
#elif defined(CONFIG_SOC_SERIES_M2L31X)
66+
case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
67+
*rate = __HXT / clkdiv_divider;
68+
break;
69+
case (CLK_CLKSEL0_CANFD0SEL_HIRC48M >> CLK_CLKSEL0_CANFD0SEL_Pos):
70+
*rate = __HIRC48 / clkdiv_divider;
71+
break;
72+
case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
73+
*rate = CLK_GetHCLKFreq() / clkdiv_divider;
74+
break;
75+
case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
76+
*rate = __HIRC / clkdiv_divider;
77+
break;
78+
#endif
7079
default:
7180
LOG_ERR("Invalid clock source rate index");
7281
return -EIO;

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