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Marek Matejkartben
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soc: espressif: Fix psram0 node size and smh heap size calculation
Fixing multiple things related to psram usage: - fix conflicting psram0 dts node for all ESP32 SiP and SoC. - fix dcache and icache area used in psram mapping. - fix smh spiram heap allocations. - add `espressif,esp32-psram` compatible to set psram0 size in dts. Signed-off-by: Marek Matej <marek.matej@espressif.com>
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boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay

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/* 2MB psram */
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&psram0 {
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reg = <0x3c000000 DT_SIZE_M(2)>;
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status = "okay";
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size = <DT_SIZE_M(2)>;
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};
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#include <espressif/partitions_0x0_amp.dtsi>

boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay

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/* 2MB psram */
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&psram0 {
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reg = <0x3c000000 DT_SIZE_M(2)>;
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status = "okay";
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size = <DT_SIZE_M(2)>;
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};
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#include <espressif/partitions_0x0_amp.dtsi>

boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts

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};
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&psram0 {
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reg = <0x3f800000 DT_SIZE_M(8)>;
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status = "disabled";
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size = <DT_SIZE_M(8)>;
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};
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&uart0 {
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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: ESP32 Family pseudo-static RAM controller
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compatible: "espressif,esp32-psram"
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include: base.yaml
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properties:
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size:
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type: int
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required: true

dts/xtensa/espressif/esp32/esp32_common.dtsi

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zephyr,memory-region = "SRAM2";
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};
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dcache0: dcache0@3f400000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x3f400000 DT_SIZE_M(4)>;
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zephyr,memory-region = "DCACHE0";
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};
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dcache1: dcache1@3f800000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x3f800000 DT_SIZE_M(4)>;
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zephyr,memory-region = "DCACHE1";
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psram0: psram0 {
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compatible = "espressif,esp32-psram";
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size = <0x0>;
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};
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};
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icache0: icache0@400d0000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x400d0000 DT_SIZE_K(11456)>;
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zephyr,memory-region = "ICACHE0";
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};
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ipmmem0: memory@3ffe5230 {
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compatible = "mmio-sram";
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reg = <0x3ffe5230 0x400>;
@@ -189,14 +212,6 @@
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};
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};
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psram0: psram@3f800000 {
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device_type = "memory";
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compatible = "mmio-sram";
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/* PSRAM size is specified in SOC/SIP dtsi */
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reg = <0x3f800000 DT_SIZE_M(2)>;
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status = "disabled";
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};
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ipi0: ipi@3f4c0058 {
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compatible = "espressif,crosscore-interrupt";
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reg = <0x3f4c0058 0x4>;

dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi

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/* 2MB psram */
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&psram0 {
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reg = <0x3f800000 DT_SIZE_M(2)>;
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status = "okay";
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size = <DT_SIZE_M(2)>;
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};

dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi

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/* 2MB psram */
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&psram0 {
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reg = <0x3f800000 DT_SIZE_M(2)>;
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status = "okay";
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size = <DT_SIZE_M(2)>;
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};

dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi

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/* 2MB psram */
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&psram0 {
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reg = <0x3f800000 DT_SIZE_M(2)>;
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status = "okay";
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size = <DT_SIZE_M(2)>;
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};

dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi

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/* 4MB psram */
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&psram0 {
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reg = <0x3f800000 DT_SIZE_M(4)>;
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status = "okay";
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size = <DT_SIZE_M(4)>;
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};

dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi

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/* 8MB psram */
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&psram0 {
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reg = <0x3f800000 DT_SIZE_M(8)>;
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status = "okay";
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size = <DT_SIZE_M(8)>;
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};

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