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| 1 | +/* |
| 2 | + * Copyright (c) 2024 Renesas Electronics Corporation |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#define DT_DRV_COMPAT renesas_rz_ext_irq |
| 8 | + |
| 9 | +#include <zephyr/device.h> |
| 10 | +#include <zephyr/devicetree.h> |
| 11 | +#include <zephyr/kernel.h> |
| 12 | +#include <zephyr/irq.h> |
| 13 | +#include <zephyr/drivers/pinctrl.h> |
| 14 | +#include <zephyr/logging/log.h> |
| 15 | +#include <instances/rzg/r_intc_irq.h> |
| 16 | +#include <instances/rzg/r_intc_nmi.h> |
| 17 | +#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h> |
| 18 | + |
| 19 | +LOG_MODULE_REGISTER(rz_ext_irq, CONFIG_INTC_LOG_LEVEL); |
| 20 | + |
| 21 | +struct intc_rz_ext_irq_config { |
| 22 | + const struct pinctrl_dev_config *pin_config; |
| 23 | + const external_irq_cfg_t *fsp_cfg; |
| 24 | + const external_irq_api_t *fsp_api; |
| 25 | +}; |
| 26 | + |
| 27 | +struct intc_rz_ext_irq_data { |
| 28 | + external_irq_ctrl_t *fsp_ctrl; |
| 29 | + intc_rz_ext_irq_callback_t callback; |
| 30 | + void *callback_data; |
| 31 | +}; |
| 32 | + |
| 33 | +/* FSP interruption handlers. */ |
| 34 | +void r_intc_irq_isr(void); |
| 35 | +void r_intc_nmi_isr(void); |
| 36 | + |
| 37 | +int intc_rz_ext_irq_enable(const struct device *dev) |
| 38 | +{ |
| 39 | + const struct intc_rz_ext_irq_config *config = dev->config; |
| 40 | + struct intc_rz_ext_irq_data *data = dev->data; |
| 41 | + fsp_err_t err = FSP_SUCCESS; |
| 42 | + |
| 43 | + err = config->fsp_api->enable(data->fsp_ctrl); |
| 44 | + |
| 45 | + if (err != FSP_SUCCESS) { |
| 46 | + return -EIO; |
| 47 | + } |
| 48 | + |
| 49 | + return 0; |
| 50 | +} |
| 51 | + |
| 52 | +int intc_rz_ext_irq_disable(const struct device *dev) |
| 53 | +{ |
| 54 | + const struct intc_rz_ext_irq_config *config = dev->config; |
| 55 | + struct intc_rz_ext_irq_data *data = dev->data; |
| 56 | + fsp_err_t err = FSP_SUCCESS; |
| 57 | + |
| 58 | + err = config->fsp_api->disable(data->fsp_ctrl); |
| 59 | + |
| 60 | + if (err != FSP_SUCCESS) { |
| 61 | + return -EIO; |
| 62 | + } |
| 63 | + |
| 64 | + return 0; |
| 65 | +} |
| 66 | + |
| 67 | +int intc_rz_ext_irq_set_callback(const struct device *dev, intc_rz_ext_irq_callback_t cb, void *arg) |
| 68 | +{ |
| 69 | + struct intc_rz_ext_irq_data *data = dev->data; |
| 70 | + |
| 71 | + data->callback = cb; |
| 72 | + data->callback_data = arg; |
| 73 | + |
| 74 | + return 0; |
| 75 | +} |
| 76 | + |
| 77 | +static int intc_rz_ext_irq_init(const struct device *dev) |
| 78 | +{ |
| 79 | + const struct intc_rz_ext_irq_config *config = dev->config; |
| 80 | + struct intc_rz_ext_irq_data *data = dev->data; |
| 81 | + fsp_err_t err = FSP_SUCCESS; |
| 82 | + int ret = 0; |
| 83 | + |
| 84 | + if (config->pin_config) { |
| 85 | + ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT); |
| 86 | + |
| 87 | + if (ret < 0) { |
| 88 | + LOG_ERR("%s: pinctrl config failed.", __func__); |
| 89 | + return ret; |
| 90 | + } |
| 91 | + } |
| 92 | + |
| 93 | + err = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg); |
| 94 | + |
| 95 | + if (err != FSP_SUCCESS) { |
| 96 | + return -EIO; |
| 97 | + } |
| 98 | + |
| 99 | + return 0; |
| 100 | +} |
| 101 | + |
| 102 | +static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args) |
| 103 | +{ |
| 104 | + const struct device *dev = (const struct device *)args->p_context; |
| 105 | + struct intc_rz_ext_irq_data *data = dev->data; |
| 106 | + |
| 107 | + if (data->callback) { |
| 108 | + data->callback(data->callback_data); |
| 109 | + } |
| 110 | +} |
| 111 | + |
| 112 | +#define EXT_IRQ_RZG_IRQ_CONNECT(index, isr, isr_nmi) \ |
| 113 | + IRQ_CONNECT(DT_INST_IRQ_BY_IDX(index, 0, irq), DT_INST_IRQ_BY_IDX(index, 0, priority), \ |
| 114 | + COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), \ |
| 115 | + (isr_nmi), (isr)), NULL, 0); |
| 116 | + |
| 117 | +#define INTC_RZG_EXT_IRQ_INIT(index) \ |
| 118 | + static const external_irq_cfg_t g_external_irq##index##_cfg = { \ |
| 119 | + .trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0), \ |
| 120 | + .filter_enable = true, \ |
| 121 | + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_1, \ |
| 122 | + .p_callback = intc_rz_ext_irq_callback, \ |
| 123 | + .p_context = DEVICE_DT_INST_GET(index), \ |
| 124 | + .p_extend = NULL, \ |
| 125 | + .ipl = DT_INST_IRQ_BY_IDX(index, 0, priority), \ |
| 126 | + .irq = DT_INST_IRQ_BY_IDX(index, 0, irq), \ |
| 127 | + COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), \ |
| 128 | + (.channel = DT_INST_IRQ_BY_IDX(index, 0, irq)), \ |
| 129 | + (.channel = DT_INST_IRQ_BY_IDX(index, 0, irq) - 1)), \ |
| 130 | + }; \ |
| 131 | + \ |
| 132 | + PINCTRL_DT_INST_DEFINE(index); \ |
| 133 | + \ |
| 134 | + struct intc_rz_ext_irq_config intc_rz_ext_irq_config##index = { \ |
| 135 | + .pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ |
| 136 | + .fsp_cfg = (external_irq_cfg_t *)&g_external_irq##index##_cfg, \ |
| 137 | + COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), ( \ |
| 138 | + .fsp_api = &g_external_irq_on_intc_nmi), ( \ |
| 139 | + .fsp_api = &g_external_irq_on_intc_irq)), \ |
| 140 | + }; \ |
| 141 | + \ |
| 142 | + COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), \ |
| 143 | + (static intc_nmi_instance_ctrl_t g_external_irq##index##_ctrl;), \ |
| 144 | + (static intc_irq_instance_ctrl_t g_external_irq##index##_ctrl;)) \ |
| 145 | + \ |
| 146 | + static struct intc_rz_ext_irq_data intc_rz_ext_irq_data##index = { \ |
| 147 | + .fsp_ctrl = (external_irq_ctrl_t *)&g_external_irq##index##_ctrl, \ |
| 148 | + }; \ |
| 149 | + \ |
| 150 | + static int intc_rz_ext_irq_init_##index(const struct device *dev) \ |
| 151 | + { \ |
| 152 | + EXT_IRQ_RZG_IRQ_CONNECT(index, r_intc_irq_isr, r_intc_nmi_isr) \ |
| 153 | + return intc_rz_ext_irq_init(dev); \ |
| 154 | + }; \ |
| 155 | + \ |
| 156 | + DEVICE_DT_INST_DEFINE(index, intc_rz_ext_irq_init_##index, NULL, \ |
| 157 | + &intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index, \ |
| 158 | + PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL); |
| 159 | + |
| 160 | +DT_INST_FOREACH_STATUS_OKAY(INTC_RZG_EXT_IRQ_INIT) |
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