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etienne-lmskartben
etienne-lms
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kartben
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drivers: clock: stm32: factorize clock selection macros
Factorize STM32_CLOCK_*_GET() and STM32_MCO_CFGR_*_GET() macros into a single series of STM32_DT_CLKSEL_*_GET() macros based on recently introduced new common macros STM32_DT_CLKSEL_*_SHIFT and STM32_DT_CLKSEL_*_MASK. Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
1 parent 7113c06 commit c7c0014

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9 files changed

+61
-82
lines changed

9 files changed

+61
-82
lines changed

‎drivers/clock_control/clock_stm32_ll_common.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -311,10 +311,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
311311
return 0;
312312
}
313313

314-
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
315-
STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
316-
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
317-
STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
314+
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
315+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
316+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
317+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
318+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
319+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
318320

319321
return 0;
320322
}

‎drivers/clock_control/clock_stm32_ll_h5.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -200,8 +200,9 @@ static inline int stm32_clock_control_configure(const struct device *dev,
200200
return err;
201201
}
202202

203-
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
204-
STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
203+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
204+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
205+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
205206

206207
return 0;
207208
}

‎drivers/clock_control/clock_stm32_ll_h7.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -448,10 +448,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
448448

449449
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
450450

451-
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
452-
STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
453-
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
454-
STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
451+
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
452+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
453+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
454+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
455+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
456+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
455457

456458
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
457459

‎drivers/clock_control/clock_stm32_ll_n6.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -253,10 +253,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
253253
return err;
254254
}
255255

256-
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
257-
STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
258-
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
259-
STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
256+
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
257+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
258+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
259+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
260+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
261+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
260262

261263
return 0;
262264
}

‎drivers/clock_control/clock_stm32_ll_u5.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -206,10 +206,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
206206
return err;
207207
}
208208

209-
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
210-
STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
211-
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
212-
STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
209+
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
210+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
211+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
212+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
213+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
214+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
213215

214216
return 0;
215217
}

‎drivers/clock_control/clock_stm32_ll_wb0.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -252,8 +252,8 @@ static inline int stm32_clock_control_configure(const struct device *dev,
252252
void *data)
253253
{
254254
struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
255-
const uint32_t shift = STM32_CLOCK_SHIFT_GET(pclken->enr);
256-
mem_addr_t reg = RCC_REG(STM32_CLOCK_REG_GET(pclken->enr));
255+
const uint32_t shift = STM32_DT_CLKSEL_SHIFT_GET(pclken->enr);
256+
mem_addr_t reg = RCC_REG(STM32_DT_CLKSEL_REG_GET(pclken->enr));
257257
int err;
258258

259259
ARG_UNUSED(dev);
@@ -265,8 +265,8 @@ static inline int stm32_clock_control_configure(const struct device *dev,
265265
return err;
266266
}
267267

268-
sys_clear_bits(reg, STM32_CLOCK_MASK_GET(pclken->enr) << shift);
269-
sys_set_bits(reg, STM32_CLOCK_VAL_GET(pclken->enr) << shift);
268+
sys_clear_bits(reg, STM32_DT_CLKSEL_MASK_GET(pclken->enr) << shift);
269+
sys_set_bits(reg, STM32_DT_CLKSEL_VAL_GET(pclken->enr) << shift);
270270

271271
return 0;
272272
}

‎drivers/clock_control/clock_stm32_ll_wba.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -120,10 +120,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
120120
return err;
121121
}
122122

123-
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
124-
STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
125-
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
126-
STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
123+
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
124+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
125+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
126+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
127+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
128+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
127129

128130
return 0;
129131
#else

‎drivers/clock_control/clock_stm32_mco.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -41,24 +41,24 @@ static int stm32_mco_init(const struct device *dev)
4141

4242
/* MCO source */
4343
sys_clear_bits(
44-
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr),
45-
STM32_MCO_CFGR_MASK_GET(pclken->enr) <<
46-
STM32_MCO_CFGR_SHIFT_GET(pclken->enr));
44+
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
45+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
46+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
4747
sys_set_bits(
48-
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr),
49-
STM32_MCO_CFGR_VAL_GET(pclken->enr) <<
50-
STM32_MCO_CFGR_SHIFT_GET(pclken->enr));
48+
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
49+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
50+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
5151

5252
#if defined(HAS_PRESCALER)
5353
/* MCO prescaler */
5454
sys_clear_bits(
55-
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(config->prescaler),
56-
STM32_MCO_CFGR_MASK_GET(config->prescaler) <<
57-
STM32_MCO_CFGR_SHIFT_GET(config->prescaler));
55+
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(config->prescaler),
56+
STM32_DT_CLKSEL_MASK_GET(config->prescaler) <<
57+
STM32_DT_CLKSEL_SHIFT_GET(config->prescaler));
5858
sys_set_bits(
59-
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(config->prescaler),
60-
STM32_MCO_CFGR_VAL_GET(config->prescaler) <<
61-
STM32_MCO_CFGR_SHIFT_GET(config->prescaler));
59+
DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(config->prescaler),
60+
STM32_DT_CLKSEL_VAL_GET(config->prescaler) <<
61+
STM32_DT_CLKSEL_SHIFT_GET(config->prescaler));
6262
#endif
6363

6464
return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);

‎include/zephyr/drivers/clock_control/stm32_clock_control.h

Lines changed: 12 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -658,68 +658,36 @@ struct stm32_pclken {
658658
/** Clock source binding accessors */
659659

660660
/**
661-
* @brief Obtain register field from clock configuration.
661+
* @brief Obtain register field from clock source selection configuration.
662662
*
663663
* @param clock clock bit field value.
664664
*/
665-
#define STM32_CLOCK_REG_GET(clock) \
666-
(((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK)
665+
#define STM32_DT_CLKSEL_REG_GET(clock) \
666+
(((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
667667

668668
/**
669-
* @brief Obtain position field from clock configuration.
669+
* @brief Obtain position field from clock source selection configuration.
670670
*
671671
* @param clock Clock bit field value.
672672
*/
673-
#define STM32_CLOCK_SHIFT_GET(clock) \
674-
(((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK)
673+
#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
674+
(((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
675675

676676
/**
677-
* @brief Obtain mask field from clock configuration.
677+
* @brief Obtain mask field from clock source selection configuration.
678678
*
679679
* @param clock Clock bit field value.
680680
*/
681-
#define STM32_CLOCK_MASK_GET(clock) \
682-
(((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK)
681+
#define STM32_DT_CLKSEL_MASK_GET(clock) \
682+
(((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
683683

684684
/**
685-
* @brief Obtain value field from clock configuration.
685+
* @brief Obtain value field from clock source selection configuration.
686686
*
687687
* @param clock Clock bit field value.
688688
*/
689-
#define STM32_CLOCK_VAL_GET(clock) \
690-
(((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK)
691-
692-
/**
693-
* @brief Obtain register field from MCO configuration.
694-
*
695-
* @param mco_cfgr MCO configuration bit field value.
696-
*/
697-
#define STM32_MCO_CFGR_REG_GET(mco_cfgr) \
698-
(((mco_cfgr) >> STM32_MCO_CFGR_REG_SHIFT) & STM32_MCO_CFGR_REG_MASK)
699-
700-
/**
701-
* @brief Obtain position field from MCO configuration.
702-
*
703-
* @param mco_cfgr MCO configuration bit field value.
704-
*/
705-
#define STM32_MCO_CFGR_SHIFT_GET(mco_cfgr) \
706-
(((mco_cfgr) >> STM32_MCO_CFGR_SHIFT_SHIFT) & STM32_MCO_CFGR_SHIFT_MASK)
707-
708-
/**
709-
* @brief Obtain mask field from MCO configuration.
710-
*
711-
* @param mco_cfgr MCO configuration bit field value.
712-
*/
713-
#define STM32_MCO_CFGR_MASK_GET(mco_cfgr) \
714-
(((mco_cfgr) >> STM32_MCO_CFGR_MASK_SHIFT) & STM32_MCO_CFGR_MASK_MASK)
715-
716-
/**
717-
* @brief Obtain value field from MCO configuration.
718-
*
719-
* @param mco_cfgr MCO configuration bit field value.
720-
*/
721-
#define STM32_MCO_CFGR_VAL_GET(mco_cfgr) \
722-
(((mco_cfgr) >> STM32_MCO_CFGR_VAL_SHIFT) & STM32_MCO_CFGR_VAL_MASK)
689+
#define STM32_DT_CLKSEL_VAL_GET(clock) \
690+
(((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
723691

724692
#if defined(STM32_HSE_CSS)
725693
/**

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