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drivers: bbram: Enable bbram driver for MC146818
Enable bbram driver for MC146818 on RPL-s platform as a child of RTC MC146818 Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
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‎boards/intel/rpl/intel_rpl_s_crb.dts

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@@ -24,5 +24,6 @@
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aliases {
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watchdog0 = &tco_wdt;
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rtc = &rtc;
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bbram = &bbram;
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};
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};

‎drivers/bbram/CMakeLists.txt

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@@ -18,3 +18,4 @@ zephyr_library_sources_ifdef(CONFIG_BBRAM_MICROCHIP_MCP7940N_EMUL bbram_microchi
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zephyr_library_sources_ifdef(CONFIG_BBRAM_XEC bbram_xec.c)
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zephyr_library_sources_ifdef(CONFIG_BBRAM_STM32 bbram_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_BBRAM_RTS5912 bbram_rts5912.c)
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zephyr_library_sources_ifdef(CONFIG_BBRAM_MOTOROLA_MC146818 bbram_mc146818.c)

‎drivers/bbram/Kconfig

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@@ -44,4 +44,6 @@ source "drivers/bbram/Kconfig.stm32"
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source "drivers/bbram/Kconfig.rts5912"
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source "drivers/bbram/Kconfig.mc146818"
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endif # BBRAM

‎drivers/bbram/Kconfig.mc146818

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# Intel SoC BBRAM configuration options
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# Copyright (c) 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BBRAM_MOTOROLA_MC146818
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bool "BBRAM driver for x86 CMOS/RTC clock's bbram"
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default y
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depends on RTC_MOTOROLA_MC146818
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depends on DT_HAS_MOTOROLA_MC146818_BBRAM_ENABLED
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help
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Enable driver for Motorola mc146818 BBRAM.

‎drivers/bbram/bbram_mc146818.c

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/*
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* Copyright (c) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Read and Write access to offset ranges 0x2A(42)-0x31(49) and 0xAA(170)-0xB1(177)
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* are lockable through BIOS setting. To access the memory in those offsets,
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* disable the Lock in BIOS through following steps.
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* Intel Advanced Menu -> PCH-IO Configuration -> Security Configuration ->
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* RTC Memory Lock -> Disable
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*/
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#define DT_DRV_COMPAT motorola_mc146818_bbram
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/bbram.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/rtc/mc146818.h>
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#define MIN_SIZE 1 /* Minimum size to write */
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#define MIN_OFFSET 0x0E /* Starting offset of memory */
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#define MAX_STD 0x7F /* Last offset of Standard memory bank */
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#define RTC_CENT 0x32 /* Offset for RTC Century Byte */
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struct bbram_mc146818_config {
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const struct device *parent;
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io_port_t std_index;
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io_port_t std_target;
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io_port_t ext_index;
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io_port_t ext_target;
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size_t mem_size;
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};
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struct bbram_mc146818_data {
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struct k_spinlock *lock;
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};
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static uint8_t std_reg_read(const struct bbram_mc146818_config *cfg, int reg)
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{
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sys_out8(reg, cfg->std_index);
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return sys_in8(cfg->std_target);
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}
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static uint8_t ext_reg_read(const struct bbram_mc146818_config *cfg, int reg)
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{
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sys_out8(reg, cfg->ext_index);
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return sys_in8(cfg->ext_target);
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}
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static void std_reg_write(const struct bbram_mc146818_config *cfg, uint8_t value, int reg)
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{
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sys_out8(reg, cfg->std_index);
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sys_out8(value, cfg->std_target);
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}
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static void ext_reg_write(const struct bbram_mc146818_config *cfg, uint8_t value, int reg)
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{
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sys_out8(reg, cfg->ext_index);
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sys_out8(value, cfg->ext_target);
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}
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static int bbram_mc146818_read(const struct device *dev, size_t offset,
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size_t size, uint8_t *data)
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{
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const struct bbram_mc146818_config *config = dev->config;
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struct bbram_mc146818_data *dev_data = dev->data;
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if (size < MIN_SIZE || offset + size > config->mem_size
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|| data == NULL) {
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return -EFAULT;
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}
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offset += MIN_OFFSET;
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k_spinlock_key_t key = k_spin_lock(dev_data->lock);
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for (size_t i = 0; i < size; i++) {
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if (offset < MAX_STD) {
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if (offset >= RTC_CENT) {
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/* RTC_CENT byte is used to store Century data for the
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* RTC time and date, so skipping read/write operation
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* to this byte.
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*/
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*(data + i) = std_reg_read(config, offset+1);
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} else {
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*(data + i) = std_reg_read(config, offset);
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}
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} else {
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*(data + i) = ext_reg_read(config, offset+1);
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}
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offset++;
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}
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k_spin_unlock(dev_data->lock, key);
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return 0;
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}
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static int bbram_mc146818_write(const struct device *dev, size_t offset,
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size_t size, const uint8_t *data)
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{
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const struct bbram_mc146818_config *config = dev->config;
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struct bbram_mc146818_data *dev_data = dev->data;
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if (size < MIN_SIZE || offset + size > config->mem_size
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|| data == NULL) {
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return -EFAULT;
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}
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offset += MIN_OFFSET;
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k_spinlock_key_t key = k_spin_lock(dev_data->lock);
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for (size_t i = 0; i < size; i++) {
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if (offset < MAX_STD) {
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if (offset >= RTC_CENT) {
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/* RTC_CENT byte is used to store Century data for the
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* RTC time and date, so skipping read/write operation
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* to this byte.
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*/
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std_reg_write(config, *(data + i), offset+1);
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} else {
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std_reg_write(config, *(data + i), offset);
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}
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} else {
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ext_reg_write(config, *(data + i), offset+1);
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}
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offset++;
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}
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k_spin_unlock(dev_data->lock, key);
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return 0;
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}
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static int bbram_mc146818_get_size(const struct device *dev, size_t *size)
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{
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const struct bbram_mc146818_config *config = dev->config;
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*size = config->mem_size;
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return 0;
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}
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static const struct bbram_driver_api bbram_mc146818_api = {
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.read = bbram_mc146818_read,
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.write = bbram_mc146818_write,
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.get_size = bbram_mc146818_get_size,
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};
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static int bbram_mc146818_init(const struct device *dev)
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{
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const struct bbram_mc146818_config *config = dev->config;
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struct bbram_mc146818_data *dev_data = dev->data;
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struct rtc_mc146818_data *parent_data = config->parent->data;
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if (!device_is_ready(config->parent)) {
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return -ENODEV;
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}
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dev_data->lock = &parent_data->lock;
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return 0;
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}
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#define BBRAM_MC146818_DEV_CFG(n) \
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static const struct bbram_mc146818_config bbram_config_##n = { \
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.parent = DEVICE_DT_GET(DT_INST_PARENT(n)), \
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.std_index = DT_REG_ADDR_BY_IDX(DT_INST_PARENT(n), 0), \
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.std_target = DT_REG_ADDR_BY_IDX(DT_INST_PARENT(n), 1), \
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.ext_index = DT_INST_REG_ADDR_BY_IDX(n, 0), \
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.ext_target = DT_INST_REG_ADDR_BY_IDX(n, 1), \
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.mem_size = DT_INST_PROP(n, size), \
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}; \
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static struct bbram_mc146818_data bbram_data_##n; \
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DEVICE_DT_INST_DEFINE(n, &bbram_mc146818_init, NULL, \
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&bbram_data_##n, &bbram_config_##n, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&bbram_mc146818_api); \
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DT_INST_FOREACH_STATUS_OKAY(BBRAM_MC146818_DEV_CFG)

‎dts/bindings/memory-controllers/motorola,mc146818-bbram.yaml

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# Copyright (c) 2025, Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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description: Motorola MC146818 compatible Real Timer Clock Battery Backed RAM
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compatible: "motorola,mc146818-bbram"
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include: base.yaml
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properties:
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reg:
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required: true
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size:
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type: int
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required: true
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description: Memory capacity in bytes.

‎dts/x86/intel/raptor_lake_s.dtsi

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interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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alarms-count = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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bbram: bbram@72 {
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compatible = "motorola,mc146818-bbram";
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reg = <0x72 0x01 0x73 0x01>;
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size = <241>;
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status = "okay";
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};
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status = "okay";
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};

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