arch/xtensa: Fix z_xtensa_cache_[flush|inv|flush_inv]_all functions

They were basically using the wrong instructions to traverse the cache
by index: `dhi`, `dhwb` and `dhwbi` instead of `dii`, `diwb` and `diwbi`
variants.

Fixes #49112.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>

Author: edersondisouza

include/zephyr/arch/xtensa/cache.h

@@ -65,17 +65,38 @@ static ALWAYS_INLINE void z_xtensa_cache_inv(void *addr, size_t bytes)
 
 static ALWAYS_INLINE void z_xtensa_cache_inv_all(void)
 {
-	z_xtensa_cache_inv(NULL, Z_DCACHE_MAX);
+#if XCHAL_DCACHE_SIZE
+	size_t step = XCHAL_DCACHE_LINESIZE;
+	size_t line;
+
+	for (line = 0; line < XCHAL_DCACHE_SIZE; line += step) {
+		__asm__ volatile("dii %0, 0" :: "r"(line));
+	}
+#endif
 }
 
 static ALWAYS_INLINE void z_xtensa_cache_flush_all(void)
 {
-	z_xtensa_cache_flush(NULL, Z_DCACHE_MAX);
+#if XCHAL_DCACHE_SIZE
+	size_t step = XCHAL_DCACHE_LINESIZE;
+	size_t line;
+
+	for (line = 0; line < XCHAL_DCACHE_SIZE; line += step) {
+		__asm__ volatile("diwb %0, 0" :: "r"(line));
+	}
+#endif
 }
 
 static ALWAYS_INLINE void z_xtensa_cache_flush_inv_all(void)
 {
-	z_xtensa_cache_flush_inv(NULL, Z_DCACHE_MAX);
+#if XCHAL_DCACHE_SIZE
+	size_t step = XCHAL_DCACHE_LINESIZE;
+	size_t line;
+
+	for (line = 0; line < XCHAL_DCACHE_SIZE; line += step) {
+		__asm__ volatile("diwbi %0, 0" :: "r"(line));
+	}
+#endif
 }