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drivers: mdio: Add Intel IGC MDIO driver support
Intel i226 MAC supports MDIO C22 and MDIO C45. Standard PHY registers are accessible through MDIO C22, whereas PMAPMD and PCS are accssible through MDIO C45. Additionaly, this commit adds extended MDIO shell support for retrieving real-time MDIO register values. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
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‎drivers/mdio/CMakeLists.txt

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@@ -20,3 +20,4 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_RENESAS_RA mdio_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_LAN865X mdio_lan865x.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_SENSRY_SY1XX mdio_sy1xx.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_XILINX_AXI_ENET mdio_xilinx_axienet.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_INTEL_IGC mdio_intel_igc.c)

‎drivers/mdio/Kconfig

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@@ -41,6 +41,7 @@ source "drivers/mdio/Kconfig.renesas_ra"
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source "drivers/mdio/Kconfig.lan865x"
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source "drivers/mdio/Kconfig.sy1xx"
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source "drivers/mdio/Kconfig.xilinx_axienet"
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source "drivers/mdio/Kconfig.intel_igc"
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config MDIO_INIT_PRIORITY
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int "Init priority"

‎drivers/mdio/Kconfig.intel_igc

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# Copyright 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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menuconfig MDIO_INTEL_IGC
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bool "Intel IGC MDIO driver"
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default y
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depends on DT_HAS_INTEL_IGC_MDIO_ENABLED
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help
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Enable Intel IGC MDIO driver.
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if MDIO_INTEL_IGC
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config MDIO_INTEL_BUSY_CHECK_TIMEOUT
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int "MDIO_INTEL_IGC busy wait timeout"
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default 10000
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help
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This timeout in microseconds, specifies the duration to wait for the
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completion of an MDIO read or write cycle.
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endif # MDIO_INTEL_IGC

‎drivers/mdio/mdio_intel_igc.c

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/*
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* Copyright (c) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_igc_mdio
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#include <zephyr/kernel.h>
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#include <zephyr/net/mdio.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/drivers/pcie/pcie.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(intel_igc_mdio, CONFIG_MDIO_LOG_LEVEL);
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#define INTEL_IGC_MDIC_OFFSET 0x00020
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#define INTEL_IGC_MDIC_DATA_MASK GENMASK(15, 0)
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#define INTEL_IGC_MDIC_REG_MASK GENMASK(20, 16)
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#define INTEL_IGC_MDIC_PHY_MASK GENMASK(25, 21)
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#define INTEL_IGC_MDIC_OP_MASK GENMASK(27, 26)
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#define INTEL_IGC_MDIC_READY BIT(28)
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#define INTEL_IGC_MMDCTRL 0xD
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#define INTEL_IGC_MMDCTRL_ACTYPE_MASK GENMASK(15, 14)
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#define INTEL_IGC_MMDCTRL_DEVAD_MASK GENMASK(4, 0)
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#define INTEL_IGC_MMDDATA 0xE
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#define INTEL_IGC_DEFAULT_DEVNUM 0
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struct intel_igc_mdio_cfg {
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const struct device *const platform;
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};
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struct intel_igc_mdio_data {
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struct k_mutex mdio_lock;
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mm_reg_t base;
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};
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static int intel_igc_mdio(struct intel_igc_mdio_data *data, uint32_t command)
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{
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uint32_t mdic = data->base + INTEL_IGC_MDIC_OFFSET;
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int ret;
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k_mutex_lock(&data->mdio_lock, K_FOREVER);
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sys_write32(command, mdic);
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/* Wait for the read or write transaction to complete */
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if (!WAIT_FOR((sys_read32(mdic) & INTEL_IGC_MDIC_READY),
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CONFIG_MDIO_INTEL_BUSY_CHECK_TIMEOUT, k_usleep(1))) {
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LOG_ERR("MDIC operation timed out");
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k_mutex_unlock(&data->mdio_lock);
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return -ETIMEDOUT;
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}
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ret = sys_read32(mdic);
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k_mutex_unlock(&data->mdio_lock);
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return ret;
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}
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static int intel_igc_mdio_read(const struct device *dev, uint8_t prtad,
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uint8_t regad, uint16_t *user_data)
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{
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struct intel_igc_mdio_data *const dev_data = dev->data;
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int ret;
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uint32_t command = FIELD_PREP(INTEL_IGC_MDIC_PHY_MASK, prtad) |
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FIELD_PREP(INTEL_IGC_MDIC_REG_MASK, regad) |
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FIELD_PREP(INTEL_IGC_MDIC_OP_MASK, MDIO_OP_C22_READ);
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ret = intel_igc_mdio(dev_data, command);
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if (ret < 0) {
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return ret;
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}
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*user_data = FIELD_GET(INTEL_IGC_MDIC_DATA_MASK, ret);
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return 0;
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}
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static int intel_igc_mdio_write(const struct device *dev, uint8_t prtad,
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uint8_t regad, uint16_t user_data)
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{
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struct intel_igc_mdio_data *const dev_data = dev->data;
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int ret;
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uint32_t command = FIELD_PREP(INTEL_IGC_MDIC_PHY_MASK, prtad) |
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FIELD_PREP(INTEL_IGC_MDIC_REG_MASK, regad) |
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FIELD_PREP(INTEL_IGC_MDIC_OP_MASK, MDIO_OP_C22_WRITE) |
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FIELD_PREP(INTEL_IGC_MDIC_DATA_MASK, user_data);
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ret = intel_igc_mdio(dev_data, command);
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return ret < 0 ? ret : 0;
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}
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static int intel_igc_mdio_pre_handle_c45(const struct device *dev, uint8_t prtad,
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uint8_t devnum, uint16_t regad)
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{
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int ret;
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/* Set device number using MMDCTRL */
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ret = intel_igc_mdio_write(dev, prtad, INTEL_IGC_MMDCTRL,
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(uint16_t)(FIELD_PREP(INTEL_IGC_MMDCTRL_DEVAD_MASK, devnum)));
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if (ret < 0) {
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return ret;
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}
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/* Set register address using MMDDATA */
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ret = intel_igc_mdio_write(dev, prtad, INTEL_IGC_MMDDATA, regad);
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if (ret < 0) {
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return ret;
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}
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/* Set device number and access type as data using MMDCTRL */
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return intel_igc_mdio_write(dev, prtad, INTEL_IGC_MMDCTRL,
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(uint16_t)(FIELD_PREP(INTEL_IGC_MMDCTRL_ACTYPE_MASK, 1) |
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FIELD_PREP(INTEL_IGC_MMDCTRL_DEVAD_MASK, devnum)));
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}
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static int intel_igc_mdio_post_handle_c45(const struct device *dev, uint8_t prtad)
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{
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/* Restore default device number using MMDCTRL */
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return intel_igc_mdio_write(dev, prtad, INTEL_IGC_MMDCTRL, INTEL_IGC_DEFAULT_DEVNUM);
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}
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static int intel_igc_mdio_read_c45(const struct device *dev, uint8_t prtad,
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uint8_t devnum, uint16_t regad, uint16_t *user_data)
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{
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int ret = intel_igc_mdio_pre_handle_c45(dev, prtad, devnum, regad);
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if (ret < 0) {
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return ret;
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}
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/* Read user data using MMDDATA */
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ret = intel_igc_mdio_read(dev, prtad, INTEL_IGC_MMDDATA, user_data);
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if (ret < 0) {
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return ret;
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}
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return intel_igc_mdio_post_handle_c45(dev, prtad);
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}
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static int intel_igc_mdio_write_c45(const struct device *dev, uint8_t prtad,
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uint8_t devnum, uint16_t regad, uint16_t user_data)
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{
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int ret = intel_igc_mdio_pre_handle_c45(dev, prtad, devnum, regad);
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if (ret < 0) {
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return ret;
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}
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/* Write the user_data using MMDDATA */
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ret = intel_igc_mdio_write(dev, prtad, INTEL_IGC_MMDDATA, user_data);
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if (ret < 0) {
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return ret;
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}
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return intel_igc_mdio_post_handle_c45(dev, prtad);
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}
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static void intel_igc_mdio_bus_enable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static void intel_igc_mdio_bus_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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}
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static const struct mdio_driver_api mdio_api = {
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.read = intel_igc_mdio_read,
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.write = intel_igc_mdio_write,
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.read_c45 = intel_igc_mdio_read_c45,
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.write_c45 = intel_igc_mdio_write_c45,
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.bus_enable = intel_igc_mdio_bus_enable,
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.bus_disable = intel_igc_mdio_bus_disable,
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};
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static int intel_igc_mdio_init(const struct device *dev)
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{
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const struct intel_igc_mdio_cfg *cfg = dev->config;
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struct intel_igc_mdio_data *data = dev->data;
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data->base = DEVICE_MMIO_GET(cfg->platform);
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return k_mutex_init(&data->mdio_lock);
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}
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#define INTEL_IGC_MDIO_INIT(n) \
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static struct intel_igc_mdio_data mdio_data_##n; \
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static struct intel_igc_mdio_cfg mdio_cfg_##n = { \
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.platform = DEVICE_DT_GET(DT_INST_PARENT(n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &intel_igc_mdio_init, NULL, &mdio_data_##n, &mdio_cfg_##n, \
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POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, &mdio_api);
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DT_INST_FOREACH_STATUS_OKAY(INTEL_IGC_MDIO_INIT)

‎drivers/mdio/mdio_shell.c

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{
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return DEVICE_API_IS(mdio, dev);
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}
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#if DT_HAS_COMPAT_STATUS_OKAY(atmel_sam_mdio)
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#define DT_DRV_COMPAT atmel_sam_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(espressif_esp32_mdio)
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#define DT_DRV_COMPAT espressif_esp32_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_imx_netc_emdio)
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#define DT_DRV_COMPAT nxp_imx_netc_emdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_netc_emdio)
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#define DT_DRV_COMPAT nxp_s32_netc_emdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_gmac_mdio)
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#define DT_DRV_COMPAT nxp_s32_gmac_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(adi_adin2111_mdio)
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#define DT_DRV_COMPAT adi_adin2111_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(smsc_lan91c111_mdio)
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#define DT_DRV_COMPAT smsc_lan91c111_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(zephyr_mdio_gpio)
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#define DT_DRV_COMPAT zephyr_mdio_gpio
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_mdio)
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#define DT_DRV_COMPAT nxp_enet_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(infineon_xmc4xxx_mdio)
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#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_qos_mdio)
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#define DT_DRV_COMPAT nxp_enet_qos_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(litex_liteeth_mdio)
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#define DT_DRV_COMPAT litex_liteeth_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
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#define DT_DRV_COMPAT st_stm32_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(snps_dwcxgmac_mdio)
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#define DT_DRV_COMPAT snps_dwcxgmac_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(sensry_sy1xx_mdio)
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#define DT_DRV_COMPAT sensry_sy1xx_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(xlnx_axi_ethernet_1_00_a_mdio)
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#define DT_DRV_COMPAT xlnx_axi_ethernet_1_00_a_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(intel_igc_mdio)
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#define DT_DRV_COMPAT intel_igc_mdio
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#else
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#error "No known devicetree compatible match for MDIO shell"
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#endif
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static void device_name_get(size_t idx, struct shell_static_entry *entry)
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{

‎dts/bindings/mdio/intel,igc-mdio.yaml

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# Copyright 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Intel IGC MDIO device.
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compatible: "intel,igc-mdio"
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include: [mdio-controller.yaml, base.yaml]

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