drivers: uart_nxp_s32_linflexd: support config via devicetree

Added support for initialization configuration via Devicetree.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>

Author: congnguyenhuu

drivers/serial/uart_nxp_s32_linflexd.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +10,7 @@
 #include <zephyr/irq.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control.h>
 
 #include <Linflexd_Uart_Ip.h>
 #include <Linflexd_Uart_Ip_Irq.h>
@@ -295,14 +296,36 @@ static int uart_nxp_s32_init(const struct device *dev)
 {
 	const struct uart_nxp_s32_config *config = dev->config;
 	int err;
+	uint32_t clock_rate;
+	Linflexd_Uart_Ip_StatusType status;
 
 	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
 	if (err < 0) {
 		return err;
 	}
 
+	if (!device_is_ready(config->clock_dev)) {
+		return -ENODEV;
+	}
+
+	err = clock_control_on(config->clock_dev, config->clock_subsys);
+	if (err) {
+		return err;
+	}
+
+	err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate);
+	if (err) {
+		return err;
+	}
+
 	Linflexd_Uart_Ip_Init(config->instance, &config->hw_cfg);
 
+	status = Linflexd_Uart_Ip_SetBaudrate(config->instance, config->hw_cfg.BaudRate,
+					      clock_rate);
+	if (status != LINFLEXD_UART_IP_STATUS_SUCCESS) {
+		return -EIO;
+	}
+
 	return 0;
 }
 
@@ -345,14 +368,30 @@ static DEVICE_API(uart, uart_nxp_s32_driver_api) = {
 
 #define UART_NXP_S32_HW_CONFIG(n)						\
 	{									\
-		.BaudRate = 115200,						\
+		.BaudRate = DT_INST_PROP(n, current_speed),			\
 		.BaudRateMantissa = 26U,					\
 		.BaudRateDivisor = 16U,						\
 		.BaudRateFractionalDivisor = 1U,				\
-		.ParityCheck = false,						\
-		.ParityType = LINFLEXD_UART_IP_PARITY_EVEN,			\
-		.StopBitsCount = LINFLEXD_UART_IP_ONE_STOP_BIT,			\
-		.WordLength = LINFLEXD_UART_IP_8_BITS,				\
+		.ParityCheck = DT_INST_ENUM_IDX(n, parity) ==			\
+				UART_CFG_PARITY_NONE ? false : true,		\
+		.ParityType = DT_INST_ENUM_IDX(n, parity) ==			\
+					UART_CFG_PARITY_ODD ?			\
+				LINFLEXD_UART_IP_PARITY_ODD :			\
+				(DT_INST_ENUM_IDX(n, parity) ==			\
+						UART_CFG_PARITY_EVEN ?		\
+					LINFLEXD_UART_IP_PARITY_ONE :		\
+					(DT_INST_ENUM_IDX(n, parity) ==		\
+							UART_CFG_PARITY_MARK ?	\
+						LINFLEXD_UART_IP_PARITY_EVEN :	\
+						LINFLEXD_UART_IP_PARITY_ZERO)),	\
+		.StopBitsCount = DT_INST_ENUM_IDX(n, stop_bits) ==		\
+						UART_CFG_STOP_BITS_1 ?		\
+					LINFLEXD_UART_IP_ONE_STOP_BIT :		\
+					LINFLEXD_UART_IP_TWO_STOP_BIT,		\
+		.WordLength = DT_INST_ENUM_IDX(n, data_bits) ==			\
+						UART_CFG_DATA_BITS_7 ?		\
+					LINFLEXD_UART_IP_7_BITS	:		\
+					LINFLEXD_UART_IP_8_BITS,		\
 		.TransferType = LINFLEXD_UART_IP_USING_INTERRUPTS,		\
 		.StateStruct = &Linflexd_Uart_Ip_apStateStructure[n],		\
 		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (			\
@@ -362,6 +401,17 @@ static DEVICE_API(uart, uart_nxp_s32_driver_api) = {
 	}
 
 #define UART_NXP_S32_INIT_DEVICE(n)						\
+	BUILD_ASSERT(DT_INST_ENUM_IDX(n, stop_bits) == UART_CFG_STOP_BITS_1 ||	\
+		DT_INST_ENUM_IDX(n, stop_bits) == UART_CFG_STOP_BITS_2,		\
+		"Node " DT_NODE_PATH(DT_DRV_INST(n))				\
+		" has unsupported stop bits configuration");			\
+	BUILD_ASSERT(DT_INST_ENUM_IDX(n, data_bits) == UART_CFG_DATA_BITS_7 ||	\
+		DT_INST_ENUM_IDX(n, data_bits) == UART_CFG_DATA_BITS_8,		\
+		"Node " DT_NODE_PATH(DT_DRV_INST(n))				\
+		" has unsupported data bits configuration");			\
+	BUILD_ASSERT(DT_INST_PROP(n, hw_flow_control) == UART_CFG_FLOW_CTRL_NONE,\
+		"Node " DT_NODE_PATH(DT_DRV_INST(n))				\
+		" has unsupported flow control configuration");			\
 	PINCTRL_DT_INST_DEFINE(n);						\
 	IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,				\
 		(static struct uart_nxp_s32_data uart_nxp_s32_data_##n;))	\
@@ -370,6 +420,9 @@ static DEVICE_API(uart, uart_nxp_s32_driver_api) = {
 		.base = (LINFLEXD_Type *)DT_INST_REG_ADDR(n),			\
 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 		.hw_cfg = UART_NXP_S32_HW_CONFIG(n),				\
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
+		.clock_subsys = (clock_control_subsys_t)			\
+				DT_INST_CLOCKS_CELL(n, name),			\
 	};									\
 	static int uart_nxp_s32_init_##n(const struct device *dev)		\
 	{									\

drivers/serial/uart_nxp_s32_linflexd.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2023, 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,8 @@ struct uart_nxp_s32_config {
 	LINFLEXD_Type *base;
 	const struct pinctrl_dev_config *pincfg;
 	Linflexd_Uart_Ip_UserConfigType hw_cfg;
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
 };
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN

dts/arm/nxp/nxp_s32z27x_r52.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -125,90 +125,103 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40170000 0x1000>;
 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN0_CLK>;
 			status = "disabled";
 		};
 
 		uart1: uart@40180000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40180000 0x1000>;
 			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN1_CLK>;
 			status = "disabled";
 		};
 
 		uart2: uart@40190000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40190000 0x1000>;
 			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN2_CLK>;
 			status = "disabled";
 		};
 
 		uart3: uart@40970000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40970000 0x1000>;
 			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN3_CLK>;
 			status = "disabled";
 		};
 
 		uart4: uart@40980000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40980000 0x1000>;
 			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN4_CLK>;
 			status = "disabled";
 		};
 
 		uart5: uart@40990000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40990000 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN5_CLK>;
 			status = "disabled";
 		};
 
 		uart6: uart@42170000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42170000 0x1000>;
 			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN6_CLK>;
 			status = "disabled";
 		};
 
 		uart7: uart@42180000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42180000 0x1000>;
 			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN7_CLK>;
 			status = "disabled";
 		};
 
 		uart8: uart@42190000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42190000 0x1000>;
 			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN8_CLK>;
 			status = "disabled";
 		};
 
 		uart9: uart@42980000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42980000 0x1000>;
 			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN9_CLK>;
 			status = "disabled";
 		};
 
 		uart10: uart@42990000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42990000 0x1000>;
 			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN10_CLK>;
 			status = "disabled";
 		};
 
 		uart11: uart@429a0000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x429a0000 0x1000>;
 			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN11_CLK>;
 			status = "disabled";
 		};
 
 		uart12: uart@40330000 {
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40330000 0x1000>;
 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_MSCLIN_CLK>;
 			status = "disabled";
 		};
 

dts/bindings/serial/nxp,s32-linflexd.yaml

@@ -1,4 +1,4 @@
-# Copyright 2022 NXP
+# Copyright 2022, 2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP S32 LINFlexD
@@ -19,3 +19,21 @@ properties:
 
   pinctrl-names:
     required: true
+
+  clocks:
+    required: true
+
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8