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VynDragonVynDragon
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soc: wch: Reorganize Qingke V4 Socs for future
Reorganization for deduplication. Signed-off-by: Camille BAUD <mail@massdriver.space>
1 parent 3a962aa commit b8cca14

26 files changed

+29
-174
lines changed

‎drivers/clock_control/clock_control_wch_rcc.c

Lines changed: 1 addition & 1 deletion
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@@ -90,7 +90,7 @@ static void clock_control_wch_rcc_setup_flash(void)
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} else {
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latency = FLASH_ACTLR_LATENCY_1;
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}
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#elif defined(CONFIG_SOC_SERIES_CH32V00X)
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#elif defined(CONFIG_SOC_SERIES_QINGKE_V2A)
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if (WCH_RCC_SYSCLK <= 15000000) {
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latency = FLASH_ACTLR_LATENCY_0;
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} else if (WCH_RCC_SYSCLK <= 24000000) {

‎drivers/timer/Kconfig.wch_ch32v00x

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@@ -2,7 +2,7 @@
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# SPDX-License-Identifier: Apache-2.0
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config CH32V00X_SYSTICK
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bool "CH32V QingKe core systick timer"
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depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4C || SOC_SERIES_CH32V00X
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bool "CH32V00X systick timer"
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depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4
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default y
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depends on DT_HAS_WCH_SYSTICK_ENABLED

‎modules/hal_wch/ch32fun.h

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@@ -7,18 +7,14 @@
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#ifndef _CH32FUN_H
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#define _CH32FUN_H
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#if defined(CONFIG_SOC_CH32V003)
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#if defined(CONFIG_SOC_CH32V003) || defined(CONFIG_SOC_CH32V006)
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#define CH32V003 1
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#include <ch32v003fun.h>
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#endif
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#if defined(CONFIG_SOC_SERIES_CH32V00X)
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#define CH32V003 1
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#include <ch32v003fun.h>
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#endif
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#if defined(CONFIG_SOC_SERIES_QINGKE_V4C)
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#if defined(CONFIG_SOC_CH32V208)
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#define CH32V20x 1
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#define CH32V20x_D8W 1
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#include <ch32v003fun.h>
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#endif
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‎soc/wch/ch32v/ch32v00x/Kconfig

Lines changed: 0 additions & 9 deletions
This file was deleted.

‎soc/wch/ch32v/ch32v00x/Kconfig.defconfig

Lines changed: 0 additions & 14 deletions
This file was deleted.

‎soc/wch/ch32v/ch32v00x/Kconfig.soc

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This file was deleted.

‎soc/wch/ch32v/ch32v00x/soc_irq.S

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This file was deleted.

‎soc/wch/ch32v/ch32v00x/vector.S

Lines changed: 0 additions & 29 deletions
This file was deleted.

‎soc/wch/ch32v/qingke_v2a/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -6,3 +6,4 @@ config SOC_SERIES_QINGKE_V2A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZMMUL

‎soc/wch/ch32v/qingke_v2a/Kconfig.defconfig

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@@ -1,20 +1,11 @@
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# Copyright (c) 2024 Michael Hope
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# Copyright (c) 2024-2025 Michael Hope
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_QINGKE_V2A
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config MAIN_STACK_SIZE
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default 512
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config IDLE_STACK_SIZE
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default 256
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config ISR_STACK_SIZE
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default 256
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config CLOCK_CONTROL
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default y
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