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boards: panasonic: Update PAN B511 Evaluation Board
The PAN B511 evaluation board is a development tool for the nRF54L15 from Nordic Semiconductor. Updates are based on latest changes for nrf54l15dk. Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
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‎boards/panasonic/panb511evb/Kconfig

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# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
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# SPDX-License-Identifier: Apache-2.0
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# PANB511EVB configuration
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if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS
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DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
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config NRF_TRUSTZONE_FLASH_REGION_SIZE
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hex
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default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
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help
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This defines the flash region size from the TrustZone perspective.
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It is used when configuring the TrustZone and when setting alignments
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requirements for the partitions.
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This abstraction allows us to configure TrustZone without depending
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on peripheral-specific symbols.
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config NRF_TRUSTZONE_RAM_REGION_SIZE
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hex
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default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
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help
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This defines the RAM region size from the TrustZone perspective.
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It is used when configuring the TrustZone and when setting alignments
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requirements for the partitions.
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This abstraction allows us to configure TrustZone without depending
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on peripheral specific symbols.
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endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS

‎boards/panasonic/panb511evb/Kconfig.defconfig

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# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
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# SPDX-License-Identifier: Apache-2.0
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
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DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
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if BOARD_PANB511EVB_NRF54L15_CPUAPP
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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endif # BOARD_PANB511EVB_NRF54L15_CPUAPP
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if BOARD_PANB511EVB_NRF54L15_CPUAPP_NS
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config BT_CTLR
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default BT
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config FLASH_LOAD_OFFSET
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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config FLASH_LOAD_SIZE
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default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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# By default, if we build for a Non-Secure version of the board,
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# enable building with TF-M as the Secure Execution Environment.
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config BUILD_WITH_TFM
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default y
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endif # BOARD_PANB511EVB_NRF54L15_CPUAPP_NS

‎boards/panasonic/panb511evb/Kconfig.panb511evb

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# SPDX-License-Identifier: Apache-2.0
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config BOARD_PANB511EVB
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select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP
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select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP || BOARD_PANB511EVB_NRF54L15_CPUAPP_NS
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select SOC_NRF54L15_CPUFLPR if BOARD_PANB511EVB_NRF54L15_CPUFLPR || \
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BOARD_PANB511EVB_NRF54L15_CPUFLPR_XIP

‎boards/panasonic/panb511evb/board.cmake

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if(CONFIG_SOC_NRF54L15_CPUAPP)
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board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
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elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
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set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l15_cpuflpr.JLinkScript)
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board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
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board_runner_args(jlink "--device=nRF54L15_RV32")
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endif()
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if(CONFIG_BOARD_PANB511EVB_NRF54L15_CPUAPP_NS)
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set(TFM_PUBLIC_KEY_FORMAT "full")
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endif()
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if(CONFIG_TFM_FLASH_MERGED_BINARY)
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set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
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endif()
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)

‎boards/panasonic/panb511evb/board.yml

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variants:
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- name: xip
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cpucluster: cpuflpr
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- name: ns
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cpucluster: cpuapp
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runners:
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run_once:
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'--recover':
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- runners:
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- nrfjprog
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- nrfutil
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run: first
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groups:
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- boards:
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- panb511evb/nrf54l15/cpuapp
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- panb511evb/nrf54l15/cpuapp/ns
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- panb511evb/nrf54l15/cpuflpr
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- panb511evb/nrf54l15/cpuflpr/xip
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'--erase':
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- runners:
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- nrfjprog
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- jlink
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- nrfutil
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run: first
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groups:
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- boards:
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- panb511evb/nrf54l15/cpuapp
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- panb511evb/nrf54l15/cpuapp/ns
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- panb511evb/nrf54l15/cpuflpr
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- panb511evb/nrf54l15/cpuflpr/xip
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'--reset':
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- runners:
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- nrfjprog
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- jlink
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- nrfutil
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run: last
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groups:
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- boards:
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- panb511evb/nrf54l15/cpuapp
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- panb511evb/nrf54l15/cpuapp/ns
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- panb511evb/nrf54l15/cpuflpr
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- panb511evb/nrf54l15/cpuflpr/xip

‎boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi

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low-power-enable;
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};
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};
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/*
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* Note that P0.04 is the dedicated pin to output the LFCLK
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* (32 KHz clock). Add the following line:
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* <NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>
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* to the grtc_default and grtc_sleep node.
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* Note that this may will affect the uart30 (CTS) functionality.
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*/
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/omit-if-no-ref/ grtc_default: grtc_default {
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group1 {
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psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>;
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};
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};
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/omit-if-no-ref/ grtc_sleep: grtc_sleep {
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group1 {
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psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>;
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low-power-enable;
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};
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};
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};

‎boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml

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supported:
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- adc
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- counter
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- dmic
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- gpio
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- i2c
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- pwm

‎boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi

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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15500>;
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load-capacitance-femtofarad = <15000>;
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};
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&hfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15000>;
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load-capacitance-femtofarad = <16000>;
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};
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&regulators {

‎boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig

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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y
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# MPU-based null-pointer dereferencing detection cannot
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# be applied as the (0x0 - 0x400) is unmapped for this target.
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable Cache
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_EXTERNAL_CACHE=y
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# Start SYSCOUNTER on driver init
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CONFIG_NRF_GRTC_START_SYSCOUNTER=y

‎boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_ns.dts

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/*
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* Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#define USE_NON_SECURE_ADDRESS_MAP 1
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#include <nordic/nrf54l15_cpuapp.dtsi>
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#include "panb511evb_nrf54l15_cpuapp_common.dtsi"
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/ {
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model = "Panasonic PAN B511 EVB nRF54L15 Application MCU";
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compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuapp";
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chosen {
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zephyr,code-partition = &slot0_ns_partition;
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zephyr,sram = &sram0_ns;
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zephyr,entropy = &psa_rng;
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};
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/delete-node/ rng;
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psa_rng: psa-rng {
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status = "okay";
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};
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};
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/ {
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/*
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* Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
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* - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
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* - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
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*
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* nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
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* the FLPR MCU.
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* This static layout needs to be the same with the upstream TF-M layout in the
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* header flash_layout.h of the relevant platform. Any updates in the layout
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* needs to happen both in the flash_layout.h and in this file at the same time.
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*/
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram0_s: image_s@20000000 {
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/* Secure image memory */
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reg = <0x20000000 DT_SIZE_K(80)>;
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};
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sram0_ns: image_ns@20014000 {
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/* Non-Secure image memory */
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reg = <0x20014000 DT_SIZE_K(80)>;
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};
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};
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the
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* last 96kB are reserved for the FLPR MCU.
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*
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* This static layout needs to be the same with the upstream TF-M layout in the
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* header flash_layout.h of the relevant platform. Any updates in the layout
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* needs to happen both in the flash_layout.h and in this file at the same time.
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*/
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slot0_partition: partition@0 {
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label = "image-0";
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reg = <0x0000000 DT_SIZE_K(512)>;
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};
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tfm_ps_partition: partition@80000 {
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label = "tfm-ps";
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reg = <0x00080000 DT_SIZE_K(16)>;
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};
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tfm_its_partition: partition@84000 {
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label = "tfm-its";
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reg = <0x00084000 DT_SIZE_K(16)>;
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};
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tfm_otp_partition: partition@88000 {
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label = "tfm-otp";
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reg = <0x00088000 DT_SIZE_K(8)>;
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};
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slot0_ns_partition: partition@8A000 {
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label = "image-0-nonsecure";
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reg = <0x0008A000 DT_SIZE_K(844)>;
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};
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storage_partition: partition@15D000 {
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label = "storage";
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reg = <0x00015D000 DT_SIZE_K(32)>;
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};
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};
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};
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&uart20 {
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/* Disable so that TF-M can use this UART */
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status = "disabled";
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current-speed = <115200>;
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pinctrl-0 = <&uart20_default>;
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pinctrl-1 = <&uart20_sleep>;
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pinctrl-names = "default", "sleep";
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};

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