arch: arm: irq: allow custom irq control for multi-level interrupts

Custom irq control for multi-level interrupts should be allowed.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

Author: yangbolu1991

arch/arm/core/cortex_a_r/irq_manage.c

@@ -33,24 +33,32 @@ extern void z_arm_reserved(void);
  * Generic Interrupt Controller (GIC) and therefore the architecture interrupt
  * control functions are mapped to the GIC driver interface.
  *
+ * When GIC is used together with other interrupt controller for
+ * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS
+ * is enabled), the architecture interrupt control functions are mapped
+ * to the SoC layer in `include/arch/arm/irq.h`.
+ * The exported arm interrupt control functions which are wrappers of
+ * GIC control could be used for SoC to do level 1 irq control to implement SoC
+ * layer interrupt control functions.
+ *
  * When a custom interrupt controller is used (i.e.
  * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
  * interrupt control functions are mapped to the SoC layer in
  * `include/arch/arm/irq.h`.
  */
 
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
-void arch_irq_enable(unsigned int irq)
+void arm_irq_enable(unsigned int irq)
 {
 	arm_gic_irq_enable(irq);
 }
 
-void arch_irq_disable(unsigned int irq)
+void arm_irq_disable(unsigned int irq)
 {
 	arm_gic_irq_disable(irq);
 }
 
-int arch_irq_is_enabled(unsigned int irq)
+int arm_irq_is_enabled(unsigned int irq)
 {
 	return arm_gic_irq_is_enabled(irq);
 }
@@ -65,10 +73,11 @@ int arch_irq_is_enabled(unsigned int irq)
  * priority levels which are reserved: three for various types of exceptions,
  * and possibly one additional to support zero latency interrupts.
  */
-void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
 	arm_gic_irq_set_priority(irq, prio, flags);
 }
+
 #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
 
 void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf);

arch/arm/core/cortex_m/irq_manage.c

@@ -32,19 +32,38 @@ extern void z_arm_reserved(void);
 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
 
+/*
+ * For Cortex-M core, the default interrupt controller is the ARM
+ * NVIC and therefore the architecture interrupt control functions
+ * are mapped to the NVIC driver interface.
+ *
+ * When NVIC is used together with other interrupt controller for
+ * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS
+ * is enabled), the architecture interrupt control functions are mapped
+ * to the SoC layer in `include/arch/arm/irq.h`.
+ * The exported arm interrupt control functions which are wrappers of
+ * NVIC control could be used for SoC to do level 1 irq control to implement SoC
+ * layer interrupt control functions.
+ *
+ * When a custom interrupt controller is used (i.e.
+ * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
+ * interrupt control functions are mapped to the SoC layer in
+ * `include/arch/arm/irq.h`.
+ */
+
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
 
-void arch_irq_enable(unsigned int irq)
+void arm_irq_enable(unsigned int irq)
 {
 	NVIC_EnableIRQ((IRQn_Type)irq);
 }
 
-void arch_irq_disable(unsigned int irq)
+void arm_irq_disable(unsigned int irq)
 {
 	NVIC_DisableIRQ((IRQn_Type)irq);
 }
 
-int arch_irq_is_enabled(unsigned int irq)
+int arm_irq_is_enabled(unsigned int irq)
 {
 	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
 }
@@ -58,7 +77,7 @@ int arch_irq_is_enabled(unsigned int irq)
  * of priority levels is a little complex, as there are some hardware
  * priority levels which are reserved.
  */
-void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
 	/* The kernel may reserve some of the highest priority levels.
 	 * So we offset the requested priority level with the number

include/zephyr/arch/arm/irq.h

@@ -35,20 +35,23 @@ GTEXT(z_soc_irq_eoi)
 #else
 
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
+extern void arm_irq_enable(unsigned int irq);
+extern void arm_irq_disable(unsigned int irq);
+extern int arm_irq_is_enabled(unsigned int irq);
+extern void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags);
+#if !defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
+#define arch_irq_enable(irq)                     arm_irq_enable(irq)
+#define arch_irq_disable(irq)                    arm_irq_disable(irq)
+#define arch_irq_is_enabled(irq)                 arm_irq_is_enabled(irq)
+#define z_arm_irq_priority_set(irq, prio, flags) arm_irq_priority_set(irq, prio, flags)
+#endif
+#endif
 
-extern void arch_irq_enable(unsigned int irq);
-extern void arch_irq_disable(unsigned int irq);
-extern int arch_irq_is_enabled(unsigned int irq);
-
-/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
-extern void z_arm_irq_priority_set(unsigned int irq, unsigned int prio,
-				   uint32_t flags);
-
-#else
-
+#if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) || defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
 /*
- * When a custom interrupt controller is specified, map the architecture
- * interrupt control functions to the SoC layer interrupt control functions.
+ * When a custom interrupt controller or multi-level interrupts is specified,
+ * map the architecture interrupt control functions to the SoC layer interrupt
+ * control functions.
  */
 
 void z_soc_irq_init(void);
@@ -69,7 +72,7 @@ void z_soc_irq_eoi(unsigned int irq);
 #define z_arm_irq_priority_set(irq, prio, flags)	\
 	z_soc_irq_priority_set(irq, prio, flags)
 
-#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
+#endif
 
 extern void z_arm_int_exit(void);