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Dino-Ligalak
Dino-Li
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galak
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drivers: gpio: it8xxx2: add support for GPIO_VOLTAGE_ flags
Support GPIO_VOLTAGE_1P8, GPIO_VOLTAGE_3P3 flags on IT8xxx2 chips. Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
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‎drivers/gpio/gpio_ite_it8xxx2.c

Lines changed: 144 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@ struct gpio_ite_cfg {
3131
uintptr_t reg_gpdmr;
3232
/* gpio port output type register (bit mapping to pin) */
3333
uintptr_t reg_gpotr;
34+
/* Index in gpio_1p8v for voltage level control register element. */
35+
uint8_t index;
3436
/* gpio's irq */
3537
uint8_t gpio_irq[8];
3638
};
@@ -222,6 +224,122 @@ static const struct {
222224
};
223225
BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT8XXX2_IRQ_COUNT + 1);
224226

227+
/* 1.8v gpio group a, b, c, d, e, f, g, h, i, j, k, l, and m */
228+
#define GPIO_GROUP_COUNT 13
229+
#define GPIO_GROUP_INDEX(label) \
230+
(uint8_t)(DT_REG_ADDR(DT_NODELABEL(label)) - \
231+
DT_REG_ADDR(DT_NODELABEL(gpioa)))
232+
233+
/* general control registers for selecting 1.8V/3.3V */
234+
static const struct {
235+
uint8_t offset;
236+
uint8_t mask_1p8v;
237+
} gpio_1p8v[GPIO_GROUP_COUNT][8] = {
238+
[GPIO_GROUP_INDEX(gpioa)] = {
239+
[4] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(0)},
240+
[5] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(1)},
241+
[6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(5)},
242+
[7] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(6)} },
243+
[GPIO_GROUP_INDEX(gpiob)] = {
244+
[3] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(1)},
245+
[4] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(0)},
246+
[5] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(7)},
247+
[6] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(6)},
248+
[7] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(4)} },
249+
[GPIO_GROUP_INDEX(gpioc)] = {
250+
[0] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(7)},
251+
[1] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(5)},
252+
[2] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(4)},
253+
[4] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(2)},
254+
[6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(3)},
255+
[7] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(3)} },
256+
[GPIO_GROUP_INDEX(gpiod)] = {
257+
[0] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(2)},
258+
[1] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(1)},
259+
[2] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(0)},
260+
[3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(7)},
261+
[4] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(6)},
262+
[5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(4)},
263+
[6] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(5)},
264+
[7] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(6)} },
265+
[GPIO_GROUP_INDEX(gpioe)] = {
266+
[0] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(5)},
267+
[1] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(6)},
268+
[2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(7)},
269+
[4] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(2)},
270+
[5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(3)},
271+
[6] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(4)},
272+
[7] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(3)} },
273+
[GPIO_GROUP_INDEX(gpiof)] = {
274+
[0] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(4)},
275+
[1] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(5)},
276+
[2] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(2)},
277+
[3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(1)},
278+
[4] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(0)},
279+
[5] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(7)},
280+
[6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(6)},
281+
[7] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(5)} },
282+
[GPIO_GROUP_INDEX(gpiog)] = {
283+
[0] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(2)},
284+
[1] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(4)},
285+
[2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(3)},
286+
[6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(3)} },
287+
[GPIO_GROUP_INDEX(gpioh)] = {
288+
[0] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(2)},
289+
[1] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(1)},
290+
[2] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(0)},
291+
[5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(7)},
292+
[6] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(0)} },
293+
[GPIO_GROUP_INDEX(gpioi)] = {
294+
[0] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(3)},
295+
[1] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(4)},
296+
[2] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(5)},
297+
[3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(6)},
298+
[4] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(7)},
299+
[5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(4)},
300+
[6] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(5)},
301+
[7] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(6)} },
302+
[GPIO_GROUP_INDEX(gpioj)] = {
303+
[0] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(0)},
304+
[1] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(1)},
305+
[2] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(2)},
306+
[3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(3)},
307+
[4] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(0)},
308+
[5] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(1)},
309+
[6] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(2)},
310+
[7] = {IT8XXX2_GPIO_GCR33_OFFSET, BIT(2)} },
311+
[GPIO_GROUP_INDEX(gpiok)] = {
312+
[0] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(0)},
313+
[1] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(1)},
314+
[2] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(2)},
315+
[3] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(3)},
316+
[4] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(4)},
317+
[5] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(5)},
318+
[6] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(6)},
319+
[7] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(7)} },
320+
[GPIO_GROUP_INDEX(gpiol)] = {
321+
[0] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(0)},
322+
[1] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(1)},
323+
[2] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(2)},
324+
[3] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(3)},
325+
[4] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(4)},
326+
[5] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(5)},
327+
[6] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(6)},
328+
[7] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(7)} },
329+
/*
330+
* M group's voltage level is according to chip's VCC is connected
331+
* to 1.8V or 3.3V.
332+
*/
333+
[GPIO_GROUP_INDEX(gpiom)] = {
334+
[0] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
335+
[1] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
336+
[2] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
337+
[3] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
338+
[4] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
339+
[5] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
340+
[6] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)} },
341+
};
342+
225343
/**
226344
* Driver functions
227345
*/
@@ -234,8 +352,13 @@ static int gpio_ite_configure(const struct device *dev,
234352
volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
235353
volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);
236354
volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
355+
volatile uint8_t *reg_1p8v;
356+
volatile uint8_t mask_1p8v;
237357
uint8_t mask = BIT(pin);
238358

359+
__ASSERT(gpio_config->index < GPIO_GROUP_COUNT,
360+
"Invalid GPIO group index");
361+
239362
/*
240363
* Select open drain first, so that we don't glitch the signal
241364
* when changing the line to an output.
@@ -245,6 +368,25 @@ static int gpio_ite_configure(const struct device *dev,
245368
else
246369
*reg_gpotr &= ~mask;
247370

371+
/* 1.8V or 3.3V */
372+
reg_1p8v = &IT8XXX2_GPIO_GCRX(
373+
gpio_1p8v[gpio_config->index][pin].offset);
374+
mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;
375+
if (reg_1p8v != &IT8XXX2_GPIO_GCRX(0)) {
376+
gpio_flags_t volt = flags & GPIO_VOLTAGE_MASK;
377+
378+
if (volt == GPIO_VOLTAGE_1P8) {
379+
__ASSERT(!(flags & GPIO_PULL_UP),
380+
"Don't enable internal pullup if 1.8V voltage is used");
381+
*reg_1p8v |= mask_1p8v;
382+
} else if (volt == GPIO_VOLTAGE_3P3 ||
383+
volt == GPIO_VOLTAGE_DEFAULT) {
384+
*reg_1p8v &= ~mask_1p8v;
385+
} else {
386+
return -EINVAL;
387+
}
388+
}
389+
248390
/* If output, set level before changing type to an output. */
249391
if (flags & GPIO_OUTPUT) {
250392
if (flags & GPIO_OUTPUT_INIT_HIGH)
@@ -274,11 +416,6 @@ static int gpio_ite_configure(const struct device *dev,
274416
GPCR_PORT_PIN_MODE_PULLDOWN);
275417
}
276418

277-
/*
278-
* TODO: There are some gpios are 1.8v input at default.
279-
* Is there a configuration flag for 1.8/3.3v selection.
280-
*/
281-
282419
return 0;
283420
}
284421

@@ -440,6 +577,8 @@ static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
440577
.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
441578
.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
442579
.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
580+
.index = (uint8_t)(DT_INST_REG_ADDR(inst) - \
581+
DT_REG_ADDR(DT_NODELABEL(gpioa))), \
443582
.gpio_irq[0] = DT_INST_IRQ_BY_IDX(inst, 0, irq), \
444583
.gpio_irq[1] = DT_INST_IRQ_BY_IDX(inst, 1, irq), \
445584
.gpio_irq[2] = DT_INST_IRQ_BY_IDX(inst, 2, irq), \

‎soc/riscv/riscv-ite/common/chip_chipregs.h

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1719,6 +1719,23 @@ struct flash_it8xxx2_regs {
17191719

17201720
#define IT8XXX2_GPIO_GCR ECREG(IT8XXX2_GPIO_BASE + 0x00)
17211721

1722+
#define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
1723+
#define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
1724+
#define IT8XXX2_GPIO_GCR26_OFFSET 0xd2
1725+
#define IT8XXX2_GPIO_GCR27_OFFSET 0xd3
1726+
#define IT8XXX2_GPIO_GCR28_OFFSET 0xd4
1727+
#define IT8XXX2_GPIO_GCR31_OFFSET 0xd5
1728+
#define IT8XXX2_GPIO_GCR32_OFFSET 0xd6
1729+
#define IT8XXX2_GPIO_GCR33_OFFSET 0xd7
1730+
#define IT8XXX2_GPIO_GCR19_OFFSET 0xe4
1731+
#define IT8XXX2_GPIO_GCR20_OFFSET 0xe5
1732+
#define IT8XXX2_GPIO_GCR21_OFFSET 0xe6
1733+
#define IT8XXX2_GPIO_GCR22_OFFSET 0xe7
1734+
#define IT8XXX2_GPIO_GCR23_OFFSET 0xe8
1735+
#define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
1736+
#define IT8XXX2_GPIO_GCR30_OFFSET 0xed
1737+
#define IT8XXX2_GPIO_GCR29_OFFSET 0xee
1738+
/* TODO: correct GRCx to GCRx */
17221739
#define IT8XXX2_GPIO_GRC1 ECREG(IT8XXX2_GPIO_BASE + 0xF0)
17231740
#define IT8XXX2_GPIO_GRC21 ECREG(IT8XXX2_GPIO_BASE + 0xE6)
17241741

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