Skip to content

Commit b313342

Browse files
soburikartben
soburi
authored and
kartben
committed
dts: arm: renesas: ra: Reorganize RA4M1 files
Extract common parts from `dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi` to support R7FA4M1AB3CFM. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
1 parent 64ea1b8 commit b313342

File tree

3 files changed

+369
-336
lines changed

3 files changed

+369
-336
lines changed

‎dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
/*
2+
* Copyright (c) 2025 TOKITA Hiroshi
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <zephyr/dt-bindings/clock/ra_clock.h>
8+
#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
9+
10+
/delete-node/ &ioport5;
11+
/delete-node/ &ioport6;
12+
/delete-node/ &ioport7;
13+
/delete-node/ &ioport8;
14+
15+
/ {
16+
soc {
17+
flash-controller@407e0000 {
18+
flash0: flash@0 {
19+
compatible = "soc-nv-flash";
20+
reg = <0x0 DT_SIZE_K(256)>;
21+
};
22+
};
23+
};
24+
};

‎dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi

Lines changed: 10 additions & 336 deletions
Original file line numberDiff line numberDiff line change
@@ -1,346 +1,20 @@
11
/*
22
* Copyright (c) 2024-2025 Renesas Electronics Corporation
3+
* Copyright (c) 2025 TOKITA Hiroshi
34
*
45
* SPDX-License-Identifier: Apache-2.0
56
*/
67

78
#include <zephyr/dt-bindings/clock/ra_clock.h>
8-
#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9+
#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
910

1011
/ {
11-
soc {
12-
sram0: memory@20000000 {
13-
compatible = "mmio-sram";
14-
reg = <0x20000000 DT_SIZE_K(32)>;
15-
};
16-
17-
flash-controller@407e0000 {
18-
reg = <0x407e0000 0x10000>;
19-
#address-cells = <1>;
20-
#size-cells = <1>;
21-
22-
flash0: flash@0 {
23-
compatible = "soc-nv-flash";
24-
reg = <0x0 DT_SIZE_K(256)>;
25-
};
26-
};
27-
28-
ioport6: gpio@400400c0 {
29-
compatible = "renesas,ra-gpio-ioport";
30-
reg = <0x400400c0 0x20>;
31-
port = <6>;
32-
gpio-controller;
33-
#gpio-cells = <2>;
34-
ngpios = <16>;
35-
status = "disabled";
36-
};
37-
38-
ioport7: gpio@400400e0 {
39-
compatible = "renesas,ra-gpio-ioport";
40-
reg = <0x400400e0 0x20>;
41-
port = <7>;
42-
gpio-controller;
43-
#gpio-cells = <2>;
44-
ngpios = <16>;
45-
status = "disabled";
46-
};
47-
48-
ioport8: gpio@40040100 {
49-
compatible = "renesas,ra-gpio-ioport";
50-
reg = <0x40040100 0x20>;
51-
port = <8>;
52-
gpio-controller;
53-
#gpio-cells = <2>;
54-
ngpios = <16>;
55-
status = "disabled";
56-
};
57-
58-
sci2: sci2@40070040 {
59-
compatible = "renesas,ra-sci";
60-
reg = <0x40070040 0x20>;
61-
clocks = <&pclka MSTPB 29>;
62-
status = "disabled";
63-
64-
uart {
65-
compatible = "renesas,ra-sci-uart";
66-
channel = <2>;
67-
status = "disabled";
68-
};
69-
};
70-
71-
adc@4005c000 {
72-
interrupts = <20 1>;
73-
channel-available-mask = <0x3ff7fff>;
74-
};
75-
76-
port_irq5: external-interrupt@40006005 {
77-
compatible = "renesas,ra-external-interrupt";
78-
reg = <0x40006005 0x1>;
79-
channel = <5>;
80-
renesas,sample-clock-div = <64>;
81-
#port-irq-cells = <0>;
82-
status = "disabled";
83-
};
84-
85-
port_irq8: external-interrupt@40006008 {
86-
compatible = "renesas,ra-external-interrupt";
87-
reg = <0x40006008 0x1>;
88-
channel = <8>;
89-
renesas,sample-clock-div = <64>;
90-
#port-irq-cells = <0>;
91-
status = "disabled";
92-
};
93-
94-
port_irq10: external-interrupt@4000600a {
95-
compatible = "renesas,ra-external-interrupt";
96-
reg = <0x4000600a 0x1>;
97-
channel = <10>;
98-
renesas,sample-clock-div = <64>;
99-
#port-irq-cells = <0>;
100-
status = "disabled";
101-
};
102-
103-
port_irq12: external-interrupt@4000600c {
104-
compatible = "renesas,ra-external-interrupt";
105-
reg = <0x4000600c 0x1>;
106-
channel = <12>;
107-
renesas,sample-clock-div = <64>;
108-
#port-irq-cells = <0>;
109-
status = "disabled";
110-
};
111-
112-
trng: trng {
113-
compatible = "renesas,ra-sce5-rng";
114-
status = "disabled";
115-
};
116-
117-
pwm6: pwm6@40078600 {
118-
compatible = "renesas,ra-pwm";
119-
divider = <RA_PWM_SOURCE_DIV_1>;
120-
channel = <RA_PWM_CHANNEL_6>;
121-
clocks = <&pclkd MSTPD 6>;
122-
reg = <0x40078600 0x100>;
123-
#pwm-cells = <3>;
124-
status = "disabled";
125-
};
126-
127-
pwm7: pwm7@40078700 {
128-
compatible = "renesas,ra-pwm";
129-
divider = <RA_PWM_SOURCE_DIV_1>;
130-
channel = <RA_PWM_CHANNEL_7>;
131-
clocks = <&pclkd MSTPD 6>;
132-
reg = <0x40078700 0x100>;
133-
#pwm-cells = <3>;
134-
status = "disabled";
135-
};
136-
};
137-
138-
clocks: clocks {
139-
#address-cells = <1>;
140-
#size-cells = <1>;
141-
142-
xtal: clock-main-osc {
143-
compatible = "renesas,ra-cgc-external-clock";
144-
clock-frequency = <DT_FREQ_M(12)>;
145-
#clock-cells = <0>;
146-
status = "disabled";
147-
};
148-
149-
hoco: clock-hoco {
150-
compatible = "fixed-clock";
151-
clock-frequency = <DT_FREQ_M(24)>;
152-
#clock-cells = <0>;
153-
};
154-
155-
moco: clock-moco {
156-
compatible = "fixed-clock";
157-
clock-frequency = <DT_FREQ_M(8)>;
158-
#clock-cells = <0>;
159-
};
160-
161-
loco: clock-loco {
162-
compatible = "fixed-clock";
163-
clock-frequency = <32768>;
164-
#clock-cells = <0>;
165-
};
166-
167-
subclk: clock-subclk {
168-
compatible = "renesas,ra-cgc-subclk";
169-
clock-frequency = <32768>;
170-
#clock-cells = <0>;
171-
status = "disabled";
172-
};
173-
174-
pll: pll {
175-
compatible = "renesas,ra-cgc-pll";
176-
#clock-cells = <0>;
177-
178-
clocks = <&xtal>;
179-
div = <2>;
180-
mul = <8 0>;
181-
status = "disabled";
182-
};
183-
184-
pclkblock: pclkblock@40047000 {
185-
compatible = "renesas,ra-cgc-pclk-block";
186-
reg = <0x40047000 4>,
187-
<0x40047004 4>,
188-
<0x40047008 4>;
189-
reg-names = "MSTPB", "MSTPC", "MSTPD";
190-
#clock-cells = <0>;
191-
clocks = <&pll>;
192-
status = "okay";
193-
194-
iclk: iclk {
195-
compatible = "renesas,ra-cgc-pclk";
196-
clock-frequency = <48000000>;
197-
div = <1>;
198-
#clock-cells = <2>;
199-
status = "okay";
200-
};
201-
202-
pclka: pclka {
203-
compatible = "renesas,ra-cgc-pclk";
204-
div = <1>;
205-
#clock-cells = <2>;
206-
status = "okay";
207-
};
208-
209-
pclkb: pclkb {
210-
compatible = "renesas,ra-cgc-pclk";
211-
div = <2>;
212-
#clock-cells = <2>;
213-
status = "okay";
214-
};
215-
216-
pclkc: pclkc {
217-
compatible = "renesas,ra-cgc-pclk";
218-
div = <1>;
219-
#clock-cells = <2>;
220-
status = "okay";
221-
};
222-
223-
pclkd: pclkd {
224-
compatible = "renesas,ra-cgc-pclk";
225-
div = <1>;
226-
#clock-cells = <2>;
227-
status = "okay";
228-
};
229-
230-
fclk: fclk {
231-
compatible = "renesas,ra-cgc-pclk";
232-
div = <2>;
233-
#clock-cells = <2>;
234-
status = "okay";
235-
};
236-
237-
clkout: clkout {
238-
compatible = "renesas,ra-cgc-pclk";
239-
#clock-cells = <2>;
240-
status = "disabled";
241-
};
242-
243-
uclk: uclk {
244-
compatible = "renesas,ra-cgc-pclk";
245-
#clock-cells = <2>;
246-
status = "disabled";
247-
};
248-
};
249-
};
250-
};
251-
252-
&ioport0 {
253-
port-irqs = <&port_irq2 &port_irq3 &port_irq6
254-
&port_irq7 &port_irq10 &port_irq15>;
255-
port-irq-names = "port-irq2",
256-
"port-irq3",
257-
"port-irq6",
258-
"port-irq7",
259-
"port-irq10",
260-
"port-irq15";
261-
port-irq2-pins = <2>;
262-
port-irq3-pins = <4>;
263-
port-irq6-pins = <0>;
264-
port-irq7-pins = <1 15>;
265-
port-irq10-pins = <5>;
266-
port-irq15-pins = <11>;
267-
};
268-
269-
&ioport1 {
270-
port-irqs = <&port_irq0 &port_irq1 &port_irq2
271-
&port_irq3 &port_irq4>;
272-
port-irq-names = "port-irq0",
273-
"port-irq1",
274-
"port-irq2",
275-
"port-irq3",
276-
"port-irq4";
277-
port-irq0-pins = <5>;
278-
port-irq1-pins = <1 4>;
279-
port-irq2-pins = <0>;
280-
port-irq3-pins = <10>;
281-
port-irq4-pins = <11>;
282-
};
283-
284-
&ioport2 {
285-
port-irqs = <&port_irq0 &port_irq1 &port_irq2
286-
&port_irq3>;
287-
port-irq-names = "port-irq0",
288-
"port-irq1",
289-
"port-irq2",
290-
"port-irq3";
291-
port-irq0-pins = <6>;
292-
port-irq1-pins = <5>;
293-
port-irq2-pins = <13>;
294-
port-irq3-pins = <12>;
295-
};
296-
297-
&ioport3 {
298-
port-irqs = <&port_irq5 &port_irq6 &port_irq8
299-
&port_irq9>;
300-
port-irq-names = "port-irq5",
301-
"port-irq6",
302-
"port-irq8",
303-
"port-irq9";
304-
port-irq5-pins = <2>;
305-
port-irq6-pins = <1>;
306-
port-irq8-pins = <5>;
307-
port-irq9-pins = <4>;
308-
};
309-
310-
&ioport4 {
311-
port-irqs = <&port_irq0 &port_irq4 &port_irq5
312-
&port_irq6 &port_irq7 &port_irq8
313-
&port_irq9>;
314-
port-irq-names = "port-irq0",
315-
"port-irq4",
316-
"port-irq5",
317-
"port-irq6",
318-
"port-irq7",
319-
"port-irq8",
320-
"port-irq9";
321-
port-irq0-pins = <0>;
322-
port-irq4-pins = <2 11>;
323-
port-irq5-pins = <1 10>;
324-
port-irq6-pins = <9>;
325-
port-irq7-pins = <8>;
326-
port-irq8-pins = <15>;
327-
port-irq9-pins = <14>;
328-
};
329-
330-
&ioport5 {
331-
port-irqs = <&port_irq11 &port_irq12 &port_irq14>;
332-
port-irq-names = "port-irq11",
333-
"port-irq12",
334-
"port-irq14";
335-
port-irq11-pins = <1>;
336-
port-irq12-pins = <2>;
337-
port-irq14-pins = <5>;
338-
};
339-
340-
&pwm2 {
341-
clocks = <&pclkd MSTPD 6>;
342-
};
343-
344-
&pwm3 {
345-
clocks = <&pclkd MSTPD 6>;
12+
soc {
13+
flash-controller@407e0000 {
14+
flash0: flash@0 {
15+
compatible = "soc-nv-flash";
16+
reg = <0x0 DT_SIZE_K(256)>;
17+
};
18+
};
19+
};
34620
};

0 commit comments

Comments
 (0)