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drivers: rtwdog: add NXP rtwdog driver
Port NXP rtwdog driver to Zephyr. Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
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‎boards/nxp/mimxrt1180_evk/doc/index.rst

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@@ -124,6 +124,8 @@ configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| RTWDOG | on-chip | rtwdog |
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+-----------+------------+-------------------------------------+
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The default configuration can be found in the defconfig file:
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:zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`

‎boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml

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@@ -26,4 +26,5 @@ supported:
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- i3c
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- dma
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- spi
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- watchdog
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vendor: nxp

‎drivers/watchdog/CMakeLists.txt

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@@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT8XXX2 wdt_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_LITEX wdt_litex.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MAX32 wdt_max32.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_IMX_WDOG wdt_mcux_imx_wdog.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_RTWDOG wdt_mcux_rtwdog.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG wdt_mcux_wdog.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG32 wdt_mcux_wdog32.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WWDT wdt_mcux_wwdt.c)

‎drivers/watchdog/Kconfig.mcux

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@@ -37,3 +37,10 @@ config WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG
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the number of watchdog counter ticks before timeout.
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endif # WDT_MCUX_WWDT
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config WDT_MCUX_RTWDOG
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bool "MCUX RTWDOG driver"
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default y
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depends on DT_HAS_NXP_RTWDOG_ENABLED
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help
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Enable the mcux rtwdog driver.

‎drivers/watchdog/wdt_mcux_rtwdog.c

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/*
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* Copyright 2024, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_rtwdog
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/watchdog.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys_clock.h>
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#include <fsl_rtwdog.h>
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#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(wdt_mcux_rtwdog);
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#define MSEC_TO_RTWDOG_TICKS(clock_freq, divider, msec) \
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((uint32_t)(clock_freq * msec / 1000U / divider))
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#define RTWDOG_MIN_TIMEOUT 1U
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struct mcux_rtwdog_config {
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RTWDOG_Type *base;
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uint32_t clock_frequency;
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rtwdog_clock_source_t clk_source;
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rtwdog_clock_prescaler_t clk_divider;
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void (*irq_config_func)(const struct device *dev);
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};
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struct mcux_rtwdog_data {
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wdt_callback_t callback;
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rtwdog_config_t wdog_config;
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bool timeout_valid;
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bool enabled;
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};
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static int mcux_rtwdog_setup(const struct device *dev, uint8_t options)
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{
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const struct mcux_rtwdog_config *config = dev->config;
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struct mcux_rtwdog_data *data = dev->data;
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RTWDOG_Type *base = config->base;
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if (!data->timeout_valid) {
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LOG_ERR("No valid timeouts installed");
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return -EINVAL;
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}
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if (data->enabled) {
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LOG_ERR("This watchdog has been enabled");
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return -EBUSY;
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}
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if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0U) {
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LOG_ERR("Not support WDT_OPT_PAUSE_IN_SLEEP");
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return -ENOTSUP;
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}
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data->wdog_config.workMode.enableDebug = ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U);
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RTWDOG_Init(base, &data->wdog_config);
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data->enabled = true;
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LOG_DBG("Setup the watchdog");
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return 0;
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}
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static int mcux_rtwdog_disable(const struct device *dev)
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{
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const struct mcux_rtwdog_config *config = dev->config;
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struct mcux_rtwdog_data *data = dev->data;
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RTWDOG_Type *base = config->base;
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data->timeout_valid = false;
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if (!data->enabled) {
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LOG_ERR("Disabled when watchdog is not enabled");
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return -EFAULT;
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}
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RTWDOG_Deinit(base);
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data->enabled = false;
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LOG_DBG("Disabled the watchdog");
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return 0;
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}
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static int mcux_rtwdog_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
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{
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const struct mcux_rtwdog_config *config = dev->config;
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struct mcux_rtwdog_data *data = dev->data;
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uint32_t clock_freq;
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uint32_t clk_divider;
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if (data->enabled) {
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LOG_ERR("Timeout can not be installed while watchdog has already been setup");
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return -EBUSY;
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}
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if (data->timeout_valid) {
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LOG_ERR("No more timeouts can be installed");
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return -ENOMEM;
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}
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if (cfg->flags == WDT_FLAG_RESET_NONE) {
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LOG_ERR("Not support WDT_FLAG_RESET_NONE");
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return -ENOTSUP;
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}
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RTWDOG_GetDefaultConfig(&data->wdog_config);
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clock_freq = config->clock_frequency;
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clk_divider = config->clk_divider == kRTWDOG_ClockPrescalerDivide1 ? 1U : 256U;
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data->wdog_config.clockSource = config->clk_source;
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data->wdog_config.prescaler = config->clk_divider;
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data->wdog_config.timeoutValue =
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MSEC_TO_RTWDOG_TICKS(clock_freq, clk_divider, cfg->window.max);
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if (data->wdog_config.timeoutValue > UINT16_MAX) {
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LOG_ERR("Invalid window max");
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return -EINVAL;
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}
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if (cfg->window.min != 0U) {
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data->wdog_config.enableWindowMode = true;
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data->wdog_config.windowValue =
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MSEC_TO_RTWDOG_TICKS(clock_freq, clk_divider, cfg->window.min);
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} else {
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data->wdog_config.enableWindowMode = false;
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data->wdog_config.windowValue = 0;
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}
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if ((data->wdog_config.timeoutValue < RTWDOG_MIN_TIMEOUT) ||
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(data->wdog_config.timeoutValue <= data->wdog_config.windowValue)) {
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LOG_ERR("Invalid timeout");
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return -EINVAL;
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}
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data->wdog_config.enableInterrupt = cfg->callback != NULL;
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data->callback = cfg->callback;
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data->timeout_valid = true;
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return 0;
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}
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static int mcux_rtwdog_feed(const struct device *dev, int channel_id)
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{
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const struct mcux_rtwdog_config *config = dev->config;
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struct mcux_rtwdog_data *data = dev->data;
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RTWDOG_Type *base = config->base;
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if (channel_id != 0) {
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LOG_ERR("Invalid channel id");
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return -EINVAL;
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}
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if (!data->enabled) {
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LOG_ERR("Feed disabled watchdog");
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return -EINVAL;
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}
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RTWDOG_Refresh(base);
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LOG_DBG("Fed the watchdog");
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return 0;
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}
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static void mcux_rtwdog_isr(const struct device *dev)
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{
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const struct mcux_rtwdog_config *config = dev->config;
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struct mcux_rtwdog_data *data = dev->data;
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RTWDOG_Type *base = config->base;
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RTWDOG_ClearStatusFlags(base, kRTWDOG_InterruptFlag);
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if (data->callback) {
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data->callback(dev, 0);
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}
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}
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static int mcux_rtwdog_init(const struct device *dev)
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{
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const struct mcux_rtwdog_config *config = dev->config;
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config->irq_config_func(dev);
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return 0;
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}
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static DEVICE_API(wdt, mcux_rtwdog_api) = {
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.setup = mcux_rtwdog_setup,
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.disable = mcux_rtwdog_disable,
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.install_timeout = mcux_rtwdog_install_timeout,
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.feed = mcux_rtwdog_feed,
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};
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#define TO_RTWDOG_CLK_SRC(val) _DO_CONCAT(kRTWDOG_ClockSource, val)
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#define TO_RTWDOG_CLK_DIV(val) _DO_CONCAT(kRTWDOG_ClockPrescalerDivide, val)
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#define MCUX_RTWDOG_INIT(n) \
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\
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static struct mcux_rtwdog_data mcux_rtwdog_data_##n; \
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static void mcux_rtwdog_config_func_##n(const struct device *dev); \
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\
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static const struct mcux_rtwdog_config mcux_rtwdog_config_##n = { \
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.base = (RTWDOG_Type *)DT_INST_REG_ADDR(n), \
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.irq_config_func = mcux_rtwdog_config_func_##n, \
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.clock_frequency = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
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.clk_source = TO_RTWDOG_CLK_SRC(DT_INST_PROP(n, clk_source)), \
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.clk_divider = TO_RTWDOG_CLK_DIV(DT_INST_PROP(n, clk_divider)), \
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}; \
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static void mcux_rtwdog_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_rtwdog_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}; \
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DEVICE_DT_INST_DEFINE(n, &mcux_rtwdog_init, NULL, &mcux_rtwdog_data_##n, \
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&mcux_rtwdog_config_##n, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mcux_rtwdog_api);
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DT_INST_FOREACH_STATUS_OKAY(MCUX_RTWDOG_INIT)

‎dts/arm/nxp/nxp_rt118x.dtsi

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@@ -11,6 +11,10 @@
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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aliases {
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watchdog0 = &rtwdog0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
@@ -74,6 +78,12 @@
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compatible = "nxp,imx-ccm-rev2";
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reg = <0x4450000 0x4000>;
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#clock-cells = <3>;
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lpo: lpo32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
86+
};
7787
};
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lpuart1: uart@4380000 {
@@ -1070,6 +1080,56 @@
10701080
#address-cells = <1>;
10711081
#size-cells = <0>;
10721082
};
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1084+
rtwdog0: wdog@42d0000 {
1085+
compatible = "nxp,rtwdog";
1086+
reg = <0x42d0000 0x10>;
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status = "okay";
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interrupts = <38 0>;
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clocks = <&lpo>;
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clk-source = <1>;
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clk-divider = <1>;
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};
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rtwdog1: wdog@42e0000 {
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compatible = "nxp,rtwdog";
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reg = <0x42e0000 0x10>;
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status = "disabled";
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interrupts = <39 0>;
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clocks = <&lpo>;
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clk-source = <1>;
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clk-divider = <1>;
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};
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rtwdog2: wdog@2490000 {
1105+
compatible = "nxp,rtwdog";
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reg = <0x2490000 0x10>;
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status = "disabled";
1108+
interrupts = <79 0>;
1109+
clocks = <&lpo>;
1110+
clk-source = <1>;
1111+
clk-divider = <1>;
1112+
};
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1114+
rtwdog3: wdog@24a0000 {
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compatible = "nxp,rtwdog";
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reg = <0x24a0000 0x10>;
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status = "disabled";
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interrupts = <80 0>;
1119+
clocks = <&lpo>;
1120+
clk-source = <1>;
1121+
clk-divider = <1>;
1122+
};
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rtwdog4: wdog@24b0000 {
1125+
compatible = "nxp,rtwdog";
1126+
reg = <0x24b0000 0x10>;
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status = "disabled";
1128+
interrupts = <81 0>;
1129+
clocks = <&lpo>;
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clk-source = <1>;
1131+
clk-divider = <1>;
1132+
};
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};
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10751135
&flexspi {

‎dts/bindings/watchdog/nxp,rtwdog.yaml

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# Copyright 2024, NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP RT watchdog
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compatible: "nxp,rtwdog"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
18+
required: true
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clk-source:
21+
type: int
22+
required: true
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description: Watchdog counter clock source
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clk-divider:
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type: int
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description: Watchdog counter clock divider
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required: true

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