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JiafeiPannashif
JiafeiPan
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nashif
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dts: add i.MX 943 Cortex-A Core dts
Added i.MX 943 Cortex-A Core dts file and clock binding header file. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
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‎dts/arm64/nxp/nxp_mimx943_a55.dtsi

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/clock/imx943_clock.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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gic: interrupt-controller@48000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x48000000 0x10000>, /* GIC Dist */
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<0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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scmi_shmem0: memory@445b1000 {
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compatible = "arm,scmi-shmem";
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reg = <0x445b1000 0x80>;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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shmem = <&scmi_shmem0>;
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mboxes = <&mu2 0>;
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mbox-names = "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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compatible = "arm,scmi-clock";
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_iomuxc: protocol@19 {
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compatible = "arm,scmi-pinctrl";
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reg = <0x19>;
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pinctrl: pinctrl {
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compatible = "nxp,imx943-pinctrl", "nxp,imx93-pinctrl";
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};
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};
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};
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};
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lpuart3: serial@42570000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42570000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART3>;
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status = "disabled";
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};
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lpuart4: serial@42580000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42580000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART4>;
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status = "disabled";
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};
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lpuart5: serial@42590000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42590000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART5>;
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status = "disabled";
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};
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lpuart6: serial@425a0000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x425a0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART6>;
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status = "disabled";
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};
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lpuart7: serial@42690000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42690000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART7>;
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status = "disabled";
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};
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lpuart8: serial@426a0000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x426a0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART8>;
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status = "disabled";
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};
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lpuart9: serial@42a50000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a50000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART9>;
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status = "disabled";
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};
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lpuart10: serial@42a60000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a60000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART10>;
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status = "disabled";
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};
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lpuart11: serial@42a70000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a70000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART11>;
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status = "disabled";
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};
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lpuart12: serial@42a80000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x42a80000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART12>;
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status = "disabled";
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};
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mu1: mbox@44220000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x44220000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x44380000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART1>;
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "nxp,imx-lpuart", "nxp,lpuart";
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reg = <0x44390000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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clocks = <&scmi_clk IMX943_CLK_LPUART2>;
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status = "disabled";
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};
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mu2: mbox@445b0000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x445b0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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};
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mu3: mbox@445d0000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x445d0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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mu4: mbox@445f0000 {
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compatible = "nxp,mbox-imx-mu";
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reg = <0x445f0000 DT_SIZE_K(64)>;
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interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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rx-channels = <4>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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};

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