Skip to content

Commit afe3075

Browse files
ZhaoQiang-b45475ZhaoQiang-b45475
committed
drivers: adc: add support sar adc driver
Add driver for the SAR ADC Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
1 parent 732a3a5 commit afe3075

File tree

5 files changed

+293
-0
lines changed

5 files changed

+293
-0
lines changed

‎drivers/adc/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
1313
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
1414
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_mcux_12b1msps_sar.c)
1515
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_LPADC adc_mcux_lpadc.c)
16+
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_SAR_ADC adc_mcux_sar_adc.c)
1617
zephyr_library_sources_ifdef(CONFIG_ADC_VF610 adc_vf610.c)
1718
zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
1819
zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)

‎drivers/adc/Kconfig.mcux

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,14 @@ config ADC_MCUX_LPADC
3737
help
3838
Enable the MCUX LPADC driver.
3939

40+
config ADC_MCUX_SAR_ADC
41+
bool "MCUX SAR ADC driver"
42+
default y
43+
select ADC_CONFIGURABLE_INPUTS
44+
depends on DT_HAS_NXP_SAR_ADC_ENABLED
45+
help
46+
Enable the MCUX SAR ADC driver.
47+
4048
if ADC_MCUX_12B1MSPS_SAR || ADC_MCUX_LPADC
4149
config ADC_MCUX_ETC
4250
bool "MCUX ADC ETC driver"
@@ -123,3 +131,18 @@ config LPADC_CHANNEL_COUNT
123131

124132

125133
endif # ADC_MCUX_LPADC
134+
135+
if ADC_MCUX_SAR_ADC
136+
137+
config SAR_ADC_CHANNEL_COUNT
138+
int "SAR_ADC channel count"
139+
default 8
140+
range 1 8
141+
help
142+
Amount of hardware command channels to use, reduce to save RAM.
143+
The user can reduce this value if their application uses fewer than
144+
15 ADC channels. This value corresponds to how many of the CMD
145+
registers can be configured within the ADC.
146+
147+
148+
endif # ADC_MCUX_SAR_ADC

‎drivers/adc/adc_mcux_sar_adc.c

Lines changed: 247 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,247 @@
1+
/*
2+
* Copyright 2025 NXP
3+
*
4+
* Based on adc_mcux_sar_adc.c, which is:
5+
* Copyright 2023-2024 NXP
6+
* Copyright (c) 2020 Toby Firth
7+
*
8+
* SPDX-License-Identifier: Apache-2.0
9+
*/
10+
11+
#define DT_DRV_COMPAT nxp_sar_adc
12+
13+
#include <errno.h>
14+
#include <zephyr/drivers/adc.h>
15+
#include <zephyr/sys/util.h>
16+
#include <zephyr/drivers/clock_control.h>
17+
#include <zephyr/drivers/pinctrl.h>
18+
19+
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
20+
#include <zephyr/logging/log.h>
21+
#include <zephyr/irq.h>
22+
#include <fsl_sar_adc.h>
23+
LOG_MODULE_REGISTER(adc_mcux_sar_adc);
24+
25+
#define ADC_CONTEXT_USES_KERNEL_TIMER
26+
#include "adc_context.h"
27+
28+
struct mcux_sar_adc_config {
29+
ADC_Type *base;
30+
void (*irq_config_func)(const struct device *dev);
31+
const struct device *clock_dev;
32+
clock_control_subsys_t clock_subsys;
33+
};
34+
35+
struct mcux_sar_adc_data {
36+
const struct device *dev;
37+
struct adc_context ctx;
38+
uint16_t *buffer;
39+
uint16_t *repeat_buffer;
40+
uint32_t channels;
41+
};
42+
43+
static int mcux_sar_adc_channel_setup(const struct device *dev,
44+
const struct adc_channel_cfg *channel_cfg)
45+
{
46+
/* User may configure maximum number of active channels */
47+
if (channel_cfg->channel_id >= CONFIG_SAR_ADC_CHANNEL_COUNT) {
48+
LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
49+
return -EINVAL;
50+
}
51+
52+
if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
53+
LOG_ERR("Unsupported channel acquisition time");
54+
return -ENOTSUP;
55+
}
56+
57+
if (channel_cfg->gain != ADC_GAIN_1) {
58+
LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
59+
return -ENOTSUP;
60+
}
61+
62+
if (channel_cfg->reference != ADC_REF_INTERNAL) {
63+
LOG_ERR("Unsupported channel reference");
64+
return -ENOTSUP;
65+
}
66+
67+
return 0;
68+
}
69+
70+
static int mcux_sar_adc_start_read(const struct device *dev,
71+
const struct adc_sequence *sequence)
72+
{
73+
const struct mcux_sar_adc_config *config = dev->config;
74+
struct mcux_sar_adc_data *data = dev->data;
75+
ADC_Type *base = config->base;
76+
uint8_t channel_id;
77+
78+
if (sequence->resolution != 12) {
79+
LOG_ERR("Unsupported resolution %d", sequence->resolution);
80+
return -ENOTSUP;
81+
}
82+
83+
channel_id = CONFIG_SAR_ADC_CHANNEL_COUNT;
84+
while (channel_id-- > 0) {
85+
if (sequence->channels & BIT(channel_id)) {
86+
ADC_EnableSpecificChannelNormalConv(base, channel_id);
87+
} else {
88+
ADC_DisableSpecificChannelNormalConv(base, channel_id);
89+
}
90+
}
91+
92+
//data->channels = sequence->channels;
93+
data->buffer = sequence->buffer;
94+
95+
adc_context_start_read(&data->ctx, sequence);
96+
int error = adc_context_wait_for_completion(&data->ctx);
97+
98+
return error;
99+
}
100+
101+
static int mcux_sar_adc_read_async(const struct device *dev,
102+
const struct adc_sequence *sequence,
103+
struct k_poll_signal *async)
104+
{
105+
struct mcux_sar_adc_data *data = dev->data;
106+
int error;
107+
108+
adc_context_lock(&data->ctx, async ? true : false, async);
109+
error = mcux_sar_adc_start_read(dev, sequence);
110+
adc_context_release(&data->ctx, error);
111+
112+
return error;
113+
}
114+
115+
static int mcux_sar_adc_read(const struct device *dev,
116+
const struct adc_sequence *sequence)
117+
{
118+
return mcux_sar_adc_read_async(dev, sequence, NULL);
119+
}
120+
121+
static void adc_context_start_sampling(struct adc_context *ctx)
122+
{
123+
struct mcux_sar_adc_data *data =
124+
CONTAINER_OF(ctx, struct mcux_sar_adc_data, ctx);
125+
const struct mcux_sar_adc_config *config = data->dev->config;
126+
ADC_Type *base = config->base;
127+
128+
data->channels = ctx->sequence.channels;
129+
data->repeat_buffer = data->buffer;
130+
131+
ADC_StartConvChain(base, kADC_NormalConvOneShotMode);
132+
}
133+
134+
static void adc_context_update_buffer_pointer(struct adc_context *ctx,
135+
bool repeat_sampling)
136+
{
137+
struct mcux_sar_adc_data *data =
138+
CONTAINER_OF(ctx, struct mcux_sar_adc_data, ctx);
139+
140+
if (repeat_sampling) {
141+
data->buffer = data->repeat_buffer;
142+
}
143+
}
144+
145+
static void mcux_sar_adc_isr(const struct device *dev)
146+
{
147+
const struct mcux_sar_adc_config *config = dev->config;
148+
struct mcux_sar_adc_data *data = dev->data;
149+
ADC_Type *base = config->base;
150+
adc_conv_result_t conv_result;
151+
uint16_t channel_id;
152+
153+
154+
if (((ADC_GetConvIntStatus(base) & kADC_NormalConvChainEndIntFlag))) {
155+
ADC_ClearConvIntStatus(base, kADC_NormalConvChainEndIntFlag);
156+
}
157+
158+
if (((ADC_GetConvIntStatus(base) & kADC_NormalConvEndIntFlag))) {
159+
ADC_ClearConvIntStatus(base, kADC_NormalConvEndIntFlag);
160+
}
161+
162+
for (channel_id = 0; channel_id < CONFIG_SAR_ADC_CHANNEL_COUNT; channel_id++) {
163+
if (ADC_GetChannelConvResult(base, &conv_result, channel_id)) {
164+
data->channels &= ~BIT(channel_id);
165+
*(data->buffer++) = conv_result.convData;
166+
if (data->channels == 0) {
167+
adc_context_on_sampling_done(&data->ctx, dev);
168+
}
169+
}
170+
}
171+
}
172+
173+
static int mcux_sar_adc_init(const struct device *dev)
174+
{
175+
const struct mcux_sar_adc_config *config = dev->config;
176+
struct mcux_sar_adc_data *data = dev->data;
177+
ADC_Type *base = config->base;
178+
adc_config_t adc_config;
179+
adc_calibration_config_t calibrationConfig;
180+
181+
ADC_GetDefaultConfig(&adc_config);
182+
ADC_Init(base, &adc_config);
183+
ADC_SetConvMode(base, kADC_NormalConvOneShotMode);
184+
ADC_EnableConvInt(base, (uint32_t)kADC_NormalConvChainEndIntEnable);
185+
186+
/* Do calibration to reduce or eliminate the various error contribution effects. */
187+
calibrationConfig.enableAverage = true;
188+
calibrationConfig.sampleTime = kADC_SampleTime22;
189+
#if (defined(FSL_FEATURE_ADC_HAS_CALBISTREG) && (FSL_FEATURE_ADC_HAS_CALBISTREG==1U))
190+
calibrationConfig.averageSampleNumbers = kADC_AverageSampleNumbers32;
191+
#else
192+
calibrationConfig.averageSampleNumbers = kADC_AverageSampleNumbers512;
193+
#endif /* FSL_FEATURE_ADC_HAS_CALBISTREG */
194+
195+
if (!(ADC_DoCalibration(base, &calibrationConfig)))
196+
{
197+
LOG_WRN("Calibration failed.");
198+
}
199+
200+
config->irq_config_func(dev);
201+
data->dev = dev;
202+
203+
adc_context_unlock_unconditionally(&data->ctx);
204+
205+
return 0;
206+
}
207+
208+
static DEVICE_API(adc, mcux_sar_adc_driver_api) = {
209+
.channel_setup = mcux_sar_adc_channel_setup,
210+
.read = mcux_sar_adc_read,
211+
#ifdef CONFIG_ADC_ASYNC
212+
.read_async = mcux_sar_adc_read_async,
213+
#endif
214+
};
215+
216+
#define SAR_ADC_MCUX_INIT(n) \
217+
\
218+
static void mcux_sar_adc_config_func_##n(const struct device *dev); \
219+
\
220+
static const struct mcux_sar_adc_config mcux_sar_adc_config_##n = { \
221+
.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
222+
.irq_config_func = mcux_sar_adc_config_func_##n, \
223+
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
224+
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
225+
}; \
226+
static struct mcux_sar_adc_data mcux_sar_adc_data_##n = { \
227+
ADC_CONTEXT_INIT_TIMER(mcux_sar_adc_data_##n, ctx), \
228+
ADC_CONTEXT_INIT_LOCK(mcux_sar_adc_data_##n, ctx), \
229+
ADC_CONTEXT_INIT_SYNC(mcux_sar_adc_data_##n, ctx), \
230+
}; \
231+
\
232+
DEVICE_DT_INST_DEFINE(n, \
233+
&mcux_sar_adc_init, NULL, &mcux_sar_adc_data_##n, \
234+
&mcux_sar_adc_config_##n, POST_KERNEL, \
235+
CONFIG_ADC_INIT_PRIORITY, \
236+
&mcux_sar_adc_driver_api); \
237+
\
238+
static void mcux_sar_adc_config_func_##n(const struct device *dev) \
239+
{ \
240+
IRQ_CONNECT(DT_INST_IRQN(n), \
241+
DT_INST_IRQ(n, priority), mcux_sar_adc_isr, \
242+
DEVICE_DT_INST_GET(n), 0); \
243+
\
244+
irq_enable(DT_INST_IRQN(n)); \
245+
}
246+
247+
DT_INST_FOREACH_STATUS_OKAY(SAR_ADC_MCUX_INIT)

‎dts/bindings/adc/nxp,sar-adc.yaml

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
# Copyright 2025 NXP
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
description: NXP SAR ADC controller
5+
6+
compatible: "nxp,sar-adc"
7+
8+
include: [adc-controller.yaml]
9+
10+
properties:
11+
reg:
12+
required: true
13+
14+
interrupts:
15+
required: true
16+
17+
"#io-channel-cells":
18+
const: 1
19+
20+
io-channel-cells:
21+
- input

‎modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ endif()
1515
set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 CONFIG_MCUX_COMPONENT_driver.src_2)
1616
set_variable_ifdef(CONFIG_GPIO_MCUX_IGPIO CONFIG_MCUX_COMPONENT_driver.igpio)
1717
set_variable_ifdef(CONFIG_ADC_MCUX_LPADC CONFIG_MCUX_COMPONENT_driver.lpadc)
18+
set_variable_ifdef(CONFIG_ADC_MCUX_SAR_ADC CONFIG_MCUX_COMPONENT_driver.sar_adc)
1819
set_variable_ifdef(CONFIG_COUNTER_MCUX_CTIMER CONFIG_MCUX_COMPONENT_driver.ctimer)
1920
set_variable_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC CONFIG_MCUX_COMPONENT_driver.lpc_rtc)
2021
set_variable_ifdef(CONFIG_GLIKEY_MCUX_GLIKEY CONFIG_MCUX_COMPONENT_driver.glikey)

0 commit comments

Comments
 (0)