arch: Added initial OpenRISC architecture port

This patch adds support for the OpenRISC 1000 (or1k) architecture: a
MIPS-like open hardware ISA which was first introduced in 2000.

The thread switching implementation uses the modern Zephyr thread "switch"
architecture.

Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>

Author: jhol

MAINTAINERS.yml

@@ -5569,3 +5569,15 @@ zbus:
     - "area: llext"
   tests:
     - llext
+
+OpenRISC Arch:
+  status: maintained
+  maintainers:
+    - jhol
+  files:
+    - arch/openrisc/
+    - include/zephyr/arch/openrisc/
+  labels:
+    - "area: OpenRISC"
+  tests:
+    - arch.openrisc

arch/Kconfig

@@ -66,6 +66,16 @@ config MIPS
 	help
 	  MIPS architecture
 
+config OPENRISC
+	bool
+	select ARCH_IS_SET
+	select ATOMIC_OPERATIONS_BUILTIN
+	select BIG_ENDIAN
+	select USE_SWITCH
+	select USE_SWITCH_SUPPORTED
+	help
+	  OpenRISC architecture
+
 config SPARC
 	bool
 	select ARCH_IS_SET

arch/archs.yml

@@ -9,6 +9,8 @@ archs:
     path: mips
   - name: nios2
     path: nios2
+  - name: openrisc
+    path: openrisc
   - name: posix
     path: posix
   - name: riscv

arch/openrisc/CMakeLists.txt

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf32-or1k")
+
+add_subdirectory(core)
+zephyr_include_directories(include)

arch/openrisc/Kconfig

@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menu "OpenRISC Options"
+	depends on OPENRISC
+
+config ARCH
+	string
+	default "openrisc"
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config GEN_SW_ISR_TABLE
+	default y
+
+config NUM_IRQS
+	int
+
+endmenu

arch/openrisc/core/CMakeLists.txt

@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+
+zephyr_library_sources(
+  cpu_idle.c
+  fatal.c
+  irq_manage.c
+  isr.S
+  prep_c.c
+  reboot.c
+  switch.S
+  thread.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)

arch/openrisc/core/asm_macros.inc

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation
+ *
+ * Convenience macros for assembly code
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Convenience macros for assembly code. */
+
+
+/*
+ * Helper macro which stores the value of a register to a the address contained
+ * in a pointer register plus an immediate offset.
+ */
+
+.macro op_store_reg reg, off, ptr_reg
+	l.sw \off(\ptr_reg), \reg
+.endm
+
+
+/*
+ * Helper macro which load a value to a register from an address contained in a
+ * pointer register plus an immediate offset.
+ */
+
+.macro op_load_reg reg, off, ptr_reg
+	l.lwz \reg, \off(\ptr_reg)
+.endm

arch/openrisc/core/cpu_idle.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/irq.h>
+
+#include <zephyr/tracing/tracing.h>
+
+#include <openrisc/openriscregs.h>
+
+static ALWAYS_INLINE void openrisc_idle(unsigned int key)
+{
+	sys_trace_idle();
+
+	/* unlock interrupts */
+	irq_unlock(key);
+
+	/* wait for interrupt */
+	if (openrisc_read_spr(SPR_UPR) & SPR_UPR_PMP) {
+		openrisc_write_spr(SPR_PMR, openrisc_read_spr(SPR_PMR) | SPR_PMR_DME);
+	}
+}
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
+void arch_cpu_idle(void)
+{
+	openrisc_idle(1);
+}
+#endif
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+void arch_cpu_atomic_idle(unsigned int key)
+{
+	openrisc_idle(key);
+}
+#endif

arch/openrisc/core/fatal.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com> *
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
+
+FUNC_NORETURN void z_openrisc_fatal_error(unsigned int reason,
+					  const struct arch_esf *esf)
+{
+#ifdef CONFIG_EXCEPTION_DEBUG
+	if (esf != NULL) {
+		LOG_ERR("epcr: 0x%08x esr: 0x%08x", esf->epcr, esf->esr);
+		LOG_ERR("  r3: 0x%08x  r4: 0x%08x  r5: 0x%08x  r6: 0x%08x",
+			esf->r3, esf->r4, esf->r5, esf->r6);
+		LOG_ERR("  r7: 0x%08x  r8: 0x%08x",
+			esf->r7, esf->r8);
+		LOG_ERR(" r11: 0x%08x r12: 0x%08x",
+			esf->r11, esf->r12);
+		LOG_ERR(" r13: 0x%08x r15: 0x%08x r17: 0x%08x r19: 0x%08x",
+			esf->r13, esf->r15, esf->r17, esf->r19);
+		LOG_ERR(" r21: 0x%08x r23: 0x%08x r25: 0x%08x r27: 0x%08x",
+			esf->r21, esf->r23, esf->r25, esf->r27);
+		LOG_ERR(" r29: 0x%08x r31: 0x%08x",
+			esf->r29, esf->r31);
+	}
+#endif /* CONFIG_EXCEPTION_DEBUG */
+	z_fatal_error(reason, esf);
+	CODE_UNREACHABLE;
+}
+
+static char *reason_str(unsigned int reason)
+{
+	switch (reason) {
+	case 0x2:
+		return "Bus Error";
+	case 0x3:
+		return "Data Page Fault";
+	case 0x4:
+		return "Instruction Page Fault";
+	case 0x5:
+		return "Tick Timer";
+	case 0x6:
+		return "Alignment Exception";
+	case 0x7:
+		return "Illegal Instruction";
+	case 0x8:
+		return "External Interrupt";
+	case 0x9:
+		return "D-TLB Miss";
+	case 0xA:
+		return "I-TLB Miss";
+	case 0xB:
+		return "Range Exception";
+	case 0xC:
+		return "Syscall";
+	case 0xD:
+		return "Floating Point Exception";
+	case 0xE:
+		return "Trap";
+	default:
+		return "unknown";
+	}
+}
+
+void _Fault(struct arch_esf *esf, unsigned int reason)
+{
+	LOG_ERR("");
+	LOG_ERR(" reason: %d, %s", reason, reason_str(reason));
+
+	z_openrisc_fatal_error(K_ERR_CPU_EXCEPTION, esf);
+}

arch/openrisc/core/irq_manage.c

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+#include <kswap.h>
+
+LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
+
+
+FUNC_NORETURN void z_irq_spurious(const void *unused)
+{
+	ARG_UNUSED(unused);
+
+	LOG_ERR("Spurious interrupt detected!");
+
+	z_openrisc_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
+}
+
+void arch_irq_enable(unsigned int irq)
+{
+	const unsigned int key = irq_lock();
+
+	openrisc_write_spr(SPR_PICMR, openrisc_read_spr(SPR_PICMR) | BIT(irq));
+	irq_unlock(key);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	const unsigned int key = irq_lock();
+
+	openrisc_write_spr(SPR_PICMR, openrisc_read_spr(SPR_PICMR) & ~BIT(irq));
+	irq_unlock(key);
+};
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	return (openrisc_read_spr(SPR_PICMR) & BIT(irq)) != 0;
+}
+
+void z_openrisc_enter_irq(unsigned int irq)
+{
+	if (IS_ENABLED(CONFIG_TRACING_ISR)) {
+		sys_trace_isr_enter();
+	}
+
+	const struct _isr_table_entry *const ite = _sw_isr_table + irq;
+
+	ite->isr(ite->arg);
+
+	if (IS_ENABLED(CONFIG_TRACING_ISR)) {
+		sys_trace_isr_exit();
+	}
+}
+
+#ifdef CONFIG_DYNAMIC_INTERRUPTS
+int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
+			     void (*routine)(const void *parameter),
+			     const void *parameter, uint32_t flags)
+{
+	ARG_UNUSED(flags);
+	ARG_UNUSED(priority);
+
+	z_isr_install(irq, routine, parameter);
+	return irq;
+}
+#endif /* CONFIG_DYNAMIC_INTERRUPTS */