dts: arm: stm32 reg definition for the st,stm32-qspi compatible

The st,stm32-qspi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32F412, stm32F7, stm32L4, stm32H7, stm32WB series.
qspi is addressing max 256 MBytes from 0x90000000.

Signed-off-by: Francois Ramu <francois.ramu@st.com>

Author: FRASTM

dts/arm/st/f4/stm32f412.dtsi

@@ -214,9 +214,9 @@
 
 		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-			reg = <0xa0001000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>;
 			interrupts = <92 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
 			status = "disabled";

dts/arm/st/f7/stm32f7.dtsi

@@ -856,9 +856,9 @@
 
 		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-			reg = <0xa0001000 0x34>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa0001000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
 			interrupts = <92 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
 			status = "disabled";

dts/arm/st/h7/stm32h7.dtsi

@@ -1072,9 +1072,9 @@
 
 		quadspi: spi@52005000 {
 			compatible = "st,stm32-qspi";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-			reg = <0x52005000 0x34>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
 			interrupts = <92 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>;
 			status = "disabled";

dts/arm/st/l4/stm32l4.dtsi

@@ -266,8 +266,8 @@
 		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
 			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0xa0001000 0x400>;
+			#size-cells = <0>;
+			reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>;
 			interrupts = <71 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
 			status = "disabled";

dts/arm/st/wb/stm32wb.dtsi

@@ -496,9 +496,9 @@
 
 		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
-			#address-cells = <0x1>;
-			#size-cells = <0x1>;
-			reg = <0xa0001000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa0001000 0x400>, <0x90000000 DT_SIZE_M(256)>;
 			interrupts = <0x32 0x0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
 			status = "disabled";